Dual-Height Standard Cell Layout for Reduced Voltage Droop
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Solution Overview
Problem
Existing automated processes for creating standard cell layouts in semiconductor chips often fail to optimize for performance, power consumption, signal integrity, and process yield, particularly for non-planar devices, leading to voltage droop and signal routing congestion.
Innovation Solution
The implementation of unidirectional signal routes with dual height and half-width standard cells, along with metal one power posts placed with a contacted gate pitch (CPP) of 1, reduces voltage droop by minimizing via resistance and optimizing power rail lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If automated place-and-route processes are used for standard cell layout, then design cycle is shortened, but voltage droop increases and signal integrity deteriorates
Solution Approach 1:
The patent changes the geometric parameters of the standard cell layout, specifically reducing the contacted gate poly pitch and implementing dual-height cells with optimized power rail configurations. These parameter changes reduce via resistance and optimize current distribution, thereby reducing voltage droop while maintaining automated design efficiency
Solution Approach 2:
The patent introduces vertical dimension optimization through dual-height cells, where cells of different heights are stacked to improve power distribution. This dimensional approach allows better control of via resistance and power rail routing without increasing horizontal footprint, thus reducing voltage droop in automated designs
2Power
If power rails use long wires with multiple metal layers, then power delivery is achieved, but flexibility for cell placement is reduced and signal routing congestion increases
Solution Approach 1:
The patent segments the power distribution network into localized power rails within each standard cell rather than using long continuous wires. By dividing the power delivery function into cell-level segments, the design achieves both adequate power delivery and improved flexibility for cell placement and signal routing
Solution Approach 2:
The patent implements local power rail optimization within each standard cell, tailoring the power rail configuration to the specific cell's power consumption characteristics. This local approach allows different cells to have optimized power distributions independent of global routing constraints, enhancing placement flexibility
3Reliability
If contacted gate poly pitch is reduced, then voltage droop is reduced through minimized via resistance, but manufacturing precision requirements increase
Solution Approach 1:
The patent compensates for reduced poly pitch by utilizing vertical dimension optimization through dual-height cells. This dimensional approach distributes via connections across multiple height levels, reducing the burden on horizontal pitch while maintaining reduced voltage droop through optimized via resistance in the vertical stacking configuration
Data Source
AI summary
A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.