Dual Hydrogen Barrier Structure for Ferroelectric Memory Integration
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Solution Overview
Problem
Integration of capacitor devices with ferroelectric or paraelectric materials on the same plane as logic device interconnects is challenging due to varying thicknesses and susceptibility to hydrogen damage, making it difficult to form barrier layers effectively, especially in high-density arrays.
Innovation Solution
A dual hydrogen barrier system is implemented, comprising an insulative hydrogen barrier directly adjacent to the memory device and a conductive hydrogen barrier integrated as part of the contact electrode, along with a high-density, amorphous dielectric layer to prevent hydrogen diffusion, allowing for closer spacing between devices without the need for additional spacer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single barrier layer is formed around capacitor devices, then hydrogen protection is provided, but the spacing between devices must be large enough to accommodate the barrier layer formation process
Solution Approach 1:
The barrier system is segmented into two distinct layers: a first hydrogen barrier layer directly adjacent to the capacitor device and a second hydrogen barrier layer surrounding the first layer. This segmentation allows each layer to serve specific functions and enables tighter device spacing while maintaining effective hydrogen protection.
Solution Approach 2:
The dual barrier structure combines different material properties - the first barrier layer uses materials optimized for direct interface protection with the capacitor, while the second barrier layer uses materials optimized for lateral hydrogen diffusion blocking. This composite approach provides comprehensive protection with reduced spacing requirements.
2Productivity
If capacitor devices are integrated on the same plane as logic interconnects, then high-density integration is achieved, but hydrogen diffusion damage occurs due to proximity to hydrogen-generating processes
Solution Approach 1:
The first hydrogen barrier layer acts as an intermediary between the capacitor device and the external environment, providing a direct protection interface that blocks hydrogen diffusion pathways while allowing the capacitor to be positioned close to logic interconnects.
Solution Approach 2:
The barrier layers are formed preliminarily around the capacitor devices before subsequent hydrogen-generating processes occur during logic interconnect fabrication, preventing hydrogen diffusion damage in advance while enabling high-density integration.
3Reliability
If barrier layers are formed with conventional methods, then hydrogen protection is provided, but the process becomes complex when dealing with varying capacitor thicknesses
Solution Approach 1:
The first hydrogen barrier layer is formed with local quality optimized for direct interface protection, while the second barrier layer provides uniform lateral protection. This allows each layer to be formed with process parameters tailored to its specific function, simplifying the overall formation process despite varying capacitor thicknesses.
Solution Approach 2:
The solution moves from attempting to form a single complex three-dimensional barrier around varying thickness capacitors to forming two simpler layers: one conformal layer directly on the capacitor surfaces and another lateral barrier layer, reducing formation complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects capacitor devices from hydrogen damage, enabling the integration of high-density capacitor arrays by preventing hydrogen diffusion and allowing for tighter spacing between devices, thereby enhancing manufacturing efficiency and device performance.
Implementation Method 1
a high-density, amorphous dielectric layer to prevent hydrogen diffusion
Data Source
AI summary
A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.