Dual ILD Gap Fill for Memory Stack Arrays
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Solution Overview
Problem
Non-damascene memory device stacks in the back-end-of-line (BEOL) face challenges with gap filling using existing low dielectric constant interlayer dielectric (ILD) materials, which can lead to voids and increased parasitic capacitance due to thick encapsulation.
Innovation Solution
A dual interlayer dielectric material structure is implemented, consisting of a first void-free low-k ILD material and a second void-free low-k ILD material, which entirely fills the gaps between memory device stacks, reducing topography and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick encapsulation is used to reduce topography, then gap filling is improved, but parasitic capacitance increases
Solution Approach 1:
The encapsulation structure is divided into multiple segments with different dielectric constants. A first dielectric material with dielectric constant k1 is used in regions requiring topography reduction, while a second dielectric material with lower dielectric constant k2 (where k2 < k1) is used in regions where parasitic capacitance must be minimized. This segmentation allows each material to perform its optimal function without the drawbacks of the other.
Solution Approach 2:
Different dielectric materials are applied to different local regions of the memory device stack based on specific performance requirements. The first dielectric material is applied in regions where mechanical support and topography reduction are critical, while the second dielectric material is applied in regions where electrical performance and capacitance reduction are prioritized. This local differentiation resolves the contradiction between gap filling and parasitic capacitance.
2Object-generated harmful factors
If low dielectric constant ILD material is used, then parasitic capacitance is reduced, but gap filling capability deteriorates
Solution Approach 1:
The dielectric structure is segmented into multiple layers with different dielectric constants. The first dielectric material provides the necessary flow and gap filling capability, while the second dielectric material with lower dielectric constant provides reduced parasitic capacitance. Together, they resolve the contradiction between gap filling capability and parasitic capacitance reduction.
Solution Approach 2:
The patent employs a composite dielectric structure combining two different dielectric materials with complementary properties. The first material (higher k) contributes to gap filling and mechanical integrity, while the second material (lower k) contributes to reduced parasitic capacitance. This composite approach allows the system to achieve both gap filling and low parasitic capacitance simultaneously.
Data Source
AI summary
A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.