Dual ILO CDR Path Calibration for Stable Frequency Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In short-reach data links, injection-locked oscillator-based clock-data recovery (ILO-based CDR) faces challenges in maintaining the correct ratio of free-running frequency to data rate, particularly due to temperature drift and phase errors, leading to reduced tracking performance and inability to support data patterns with long runs of consecutive identical digits.
Innovation Solution
A short-reach data link receiver is designed with two injection-locked oscillator paths, where one path operates in clock-data recovery mode and the other in calibration mode, swapping paths at predetermined intervals to maintain the oscillator's frequency ratio to the reference clock, and adjusting signal polarities to prevent discontinuities during swaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single injection-locked oscillator path is used for clock-data recovery, then the device complexity and power consumption are reduced, but the oscillator cannot maintain accurate frequency ratio tracking due to temperature drift
Solution Approach 1:
The system divides the oscillator path into two separate paths: a first path dedicated to calibration and a second path dedicated to clock-data recovery. This segmentation allows each path to perform its specific function optimally while maintaining accurate frequency tracking through periodic calibration swaps.
Solution Approach 2:
The system performs preliminary calibration by periodically swapping between the first and second oscillator paths. The path not currently used for recovery is calibrated in advance, ensuring that when swapped in, it maintains accurate frequency ratio tracking despite temperature drift.
2Measurement precision
If phase-locked loop solutions are used to maintain frequency ratio, then tracking accuracy is improved, but additional die area and power consumption are required
Solution Approach 1:
Instead of using a complex phase-locked loop, the system creates a simplified copy mechanism using two injection-locked oscillator paths that can be swapped. This copying approach maintains frequency tracking accuracy without requiring the additional circuitry and power consumption of traditional PLL solutions.
3Adaptability or versatility
If the oscillator free-running frequency ratio to data rate is not kept constant, then temperature drift is accommodated, but tracking performance deteriorates and long runs of identical digits cannot be supported
Solution Approach 1:
The system performs preliminary calibration by periodically swapping between the first and second oscillator paths. The path not currently used for recovery is calibrated in advance, ensuring that when swapped in, it maintains accurate frequency ratio tracking despite temperature drift.
Solution Approach 2:
The system implements periodic calibration by alternating between two oscillator paths at predetermined time intervals. This periodic swapping ensures that calibration is performed regularly without continuously impacting the recovery path, maintaining both adaptability and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate FRF tracking and supports data patterns with long runs of consecutive identical digits by maintaining the oscillator's frequency ratio, reducing power consumption, and avoiding additional die area and power consumption associated with phase-locked loop solutions.
Implementation Method 1
each respective one of the first and second clock-data recovery paths may include an injection-locked oscillator configured to recover the clock by injection-locking a reference frequency to the output of the edge detector
Data Source
AI summary
A short-reach data link receiver includes an edge detector configured to generate a pulse on an edge of a data input, a first clock-data recovery path coupled to an output of the edge detector for recovering a clock and data from the output of the edge detector, a second clock-data recovery path coupled to the output of the edge detector for recovering the clock and data from the output of the edge detector, and a controller configured to alternate between the first and second clock-data recovery paths to recover the clock and data using one of the paths while calibrating the other path. The controller may swap the paths whenever calibration of one path is completed. That may include beginning calibration of the next path immediately after swapping of the paths. Alternatively, power consumption may be reduced by delaying calibration of the next path after swapping of the paths.