Dual-Input Clock Generator for Low-Jitter Accurate Synchronization
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Solution Overview
Problem
Existing frequency locked loops (FLLs) in digital audio signal processing face challenges in generating a high-quality clock signal with low jitter, especially when the input clock is of poor quality or experiences degradation, leading to noise, distortion, and spurious tones, and require minimal external components for economic implementation in integrated circuit form.
Innovation Solution
A clock generator using a frequency locked loop architecture with dual input clock signals and digital filters to generate an output clock signal, where one input clock has lower jitter and higher frequency accuracy, ensuring the output clock has minimal jitter and accurate frequency synchronization, even in intermittent or changing clock scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency locked loop is used to generate a clock signal at a multiple frequency of an existing clock signal, then the output clock frequency can be accurately controlled, but the jitter of the output clock increases due to the poor quality or degradation of the input clock
Solution Approach 1:
The patent introduces an intermediary clock signal from a separate clock source that is mixed with the degraded input clock signal. This intermediary signal acts as a mediator to restore the quality of the reference clock without compromising the frequency multiplication function, thereby reducing jitter while maintaining frequency accuracy in the output clock
Solution Approach 2:
The patent employs feedback mechanisms where the output clock is monitored and used to adjust the control signal to the numerically controlled oscillator. This closed-loop feedback ensures that frequency accuracy is maintained while the system can compensate for jitter introduced during frequency multiplication
2Reliability
If digital filters are added to reduce jitter and improve clock quality, then the audio quality improves, but the device complexity increases
Solution Approach 1:
The patent replaces complex analog filtering circuits with digital signal processing techniques implemented in software or firmware. The digital filters process the clock signal in the digital domain, achieving jitter reduction and audio quality improvement without requiring complex analog components, thereby reducing overall device complexity
Solution Approach 2:
The digital filter is designed to perform multiple functions: jitter reduction, frequency synchronization, and audio quality optimization. This multi-functional approach consolidates what would otherwise require separate circuits into a single digital processing block, reducing device complexity while achieving the desired audio quality
3Device complexity
If a predominantly digital solution is used to minimize external components, then the integrated circuit implementation becomes more economical, but achieving low jitter becomes more difficult
Solution Approach 1:
The patent introduces an intermediary analog clock source that serves as a low-jitter reference. This intermediary signal is fed into the digital frequency locked loop, allowing the system to achieve low jitter performance through digital processing while minimizing the need for external crystal oscillators or other passive components, thus maintaining economical integrated circuit implementation
4Use of energy by moving object
If the clock source changes to service different use scenarios and save power, then power consumption is reduced, but clock slippage and data synchronization issues occur
Solution Approach 1:
The patent employs feedback mechanisms that continuously monitor the phase and frequency relationship between the input data clock and the output processing clock. When clock source changes occur, the feedback loop detects the slippage and adjusts the numerically controlled oscillator to re-synchronize the clocks, ensuring data synchronization is maintained even during power-saving mode transitions
Solution Approach 2:
The system dynamically adapts its clock generation parameters based on operational requirements. During active processing, the full-frequency clock is used; during idle or power-saving modes, the system dynamically switches to lower-frequency or intermittent clocking while maintaining synchronization through the feedback-controlled numerically controlled oscillator, thus achieving both power savings and data synchronization
Data Source
AI summary
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.