Dual-Input PLL Synchronization With Short Delay Lines
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Solution Overview
Problem
In large digital phased arrays, achieving synchronization of local oscillator signals among multiple IC chips in array element tiles is challenging due to phase offsets caused by environmental changes, and traditional low-frequency synchronization systems require impractically long delay wires for synchronization.
Innovation Solution
An on-chip synchronous self-repairing system utilizing a dual-input PLL structure connected via a left-handed material transmission wire, forming a stellate or butterfly-shaped configuration, which compensates for phase shifts using DLL modules and ensures synchronization of local oscillator signals across IC chips with a low-frequency reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low-frequency reference signal is used for synchronization, then the wavelength is too long requiring impractically long delay wires, but using high-frequency signals introduces synchronization errors and instability
Solution Approach 1:
The patent changes the fundamental parameter of signal frequency from traditional low-frequency (10 MHz) to high-frequency (GHz range), fundamentally altering the wavelength characteristics. This enables the use of compact delay wires while maintaining synchronization accuracy through the PLL's ability to handle high-frequency signals with precise phase detection
Solution Approach 2:
The patent introduces a phase-locked loop (PLL) as an intermediary device that mediates between the high-frequency reference signal and the local oscillator signals. The PLL acts as a frequency translator and phase synchronizer, enabling high-frequency operation without the synchronization errors that would otherwise occur, thus resolving the contradiction between frequency and stability
2Reliability
If traditional synchronization systems are used, then phase offsets occur due to environmental changes, but implementing compensation mechanisms increases system complexity
Solution Approach 1:
The patent implements a self-service mechanism where each IC chip contains its own PLL that automatically detects and compensates for phase offsets. The system performs self-diagnosis and self-correction by continuously monitoring phase differences and adjusting local oscillator signals accordingly, eliminating the need for external compensation equipment and reducing overall system complexity
Solution Approach 2:
The patent establishes a feedback loop within each PLL where the phase detector continuously monitors the phase difference between reference and local oscillator signals, and the control voltage adjusts the VCO frequency to eliminate phase errors. This automatic feedback mechanism compensates for environmental changes without requiring complex external control systems
3Reliability
If multiple array element tiles are synchronized independently, then inter-tile synchronization errors accumulate, but centralizing control increases system complexity and reduces adaptability
Solution Approach 1:
The patent segments the synchronization function by placing an independent PLL in each IC chip across multiple array element tiles. Each PLL operates autonomously to synchronize its local oscillator with the reference signal, preventing error accumulation between tiles while maintaining overall system synchronization. This distributed architecture eliminates the need for complex centralized control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This system enables strict synchronization of RF transceiver chips in array element tiles, providing a compact, low-loss, and adaptable solution that compensates for environmental-induced phase offsets with a short physical distance and low transmission losses.
Implementation Method 1
a transmission wire based on a left-handed material is used for interconnection between the dual-input PLLs
Data Source
AI summary
The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.