Dual-Instantiation IC Soft Error Mitigation via Register Comparison
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Solution Overview
Problem
Existing soft error mitigation techniques in integrated circuits, such as triple modular redundancy, consume substantial on-chip resources, making them less desirable for resource-constrained applications.
Innovation Solution
Configuring integrated circuits with two instantiations of a user design, where register values from the first instantiation are compared to corresponding registers in the second instantiation, and if a mismatch is detected, the user designs are halted and corrected, utilizing a comparator cone, multiplexers, or look-up tables to identify and address soft errors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy is used to mitigate soft errors, then reliability is improved, but on-chip resources are consumed substantially
Solution Approach 1:
The patent extracts the redundancy comparison function from the full TMR implementation, using only two instantiations instead of three. The comparator cone selectively compares register pairs between the two instantiations to detect soft errors, removing the need for the third redundant instance while maintaining error detection capability.
Solution Approach 2:
The patent applies partial redundancy by implementing only the necessary comparison functionality between two instantiations rather than full TMR with three instances. The comparator cone performs selective comparison of critical register pairs, providing sufficient error detection without the full resource overhead of complete TMR.
2Quantity of substance
If two instantiations are used with register comparison, then on-chip resource consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the comparison function into a dedicated comparator cone that processes register pairs in stages. The comparator cone is divided into multiple stages, each comparing specific register pairs and producing comparison results that are accumulated to generate the final mismatch signal, reducing the complexity of any single comparison operation.
Solution Approach 2:
The patent introduces a comparator cone as an intermediary component between the two instantiations and the error detection logic. This intermediary structure simplifies the overall system by providing a dedicated error detection mechanism that doesn't require complex control logic or additional processing stages.
3Reliability
If register values are compared continuously, then soft error detection is improved, but operation interruption increases
Solution Approach 1:
The patent enables continuous comparison of register values between the two instantiations without interrupting the normal operation of the user design. The comparator cone operates in parallel with the user logic, continuously monitoring register pairs and generating mismatch signals immediately when soft errors occur, eliminating detection delays while allowing uninterrupted computation.
Solution Approach 2:
The patent performs preliminary comparison of register values as they are written to the registers, before any erroneous data can propagate through the system. This preliminary detection action occurs transparently in the background, allowing immediate error identification without requiring subsequent operation interruptions for error detection.
Data Source
AI summary
An integrated circuit (“IC”) (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2, RA3, RA4) are compared (102) to corresponding registers of the second instantiation (RB1, RB2, RB3, RB4). If a register pair does not match, the user designs are halted, re-loaded, and re-started.