Dual Instruction Decoder Routing for Low Latency Processing
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Solution Overview
Problem
The increased latency of instruction decoders in complex instruction set architectures leads to higher branch mis-prediction penalties and reduced instructions per clock (IPC) performance, particularly when handling mixed instruction strings that require dynamic switching between low-latency and long-latency decoders.
Innovation Solution
An arithmetic processing apparatus with a first decoder for processing instructions in a single cycle and a second decoder for processing in multiple cycles, utilizing a determination circuit to dynamically route instructions based on opcode-specific processing requirements, ensuring that simple instructions are decoded with low latency and complex instructions are handled by the appropriate decoder to maintain pipeline efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single fixed-cycle decoder is used for all instructions, then the decoding process is simplified, but complex instructions require multiple cycles leading to increased latency and reduced IPC performance
Solution Approach 1:
The decoder is segmented into two independent paths: a first decoder for simple instructions that can be decoded in a single cycle, and a second decoder for complex instructions that require multiple cycles. The determination circuit segments the instruction stream by identifying which instructions route to which decoder, allowing each decoder to be optimized for its specific instruction type rather than requiring a single complex decoder to handle all cases.
2Adaptability or versatility
If a complex instruction decoder is used to handle all instructions, then all instruction types can be processed, but the decoding latency increases for simple instructions
Solution Approach 1:
Different decoding paths are provided for different instruction types. Simple instructions are routed to the first decoder which has optimized single-cycle decoding capability, while complex instructions are routed to the second decoder which has the capability to handle multi-cycle decoding. This local optimization ensures that each instruction type receives the appropriate level of decoding complexity rather than all instructions being processed by a uniform decoder.
3Loss of time
If dynamic switching between decoders is implemented, then decoder latency is reduced for simple instructions, but the device complexity increases due to the determination circuit
Solution Approach 1:
The determination circuit performs preliminary classification of instructions before they reach the decoders. By examining the instruction opcode and determining in advance whether an instruction is simple or complex, the circuit routes the instruction to the appropriate decoder before decoding begins. This preliminary action prevents wasted decoding cycles and eliminates the need for complex runtime switching mechanisms during the actual decoding process.
Data Source
AI summary
An arithmetic processing apparatus includes two instruction decoders. A first decoder processes instructions in a single cycle, while a second decoder processes instructions in a plurality of cycles. The apparatus further includes a determination circuit that causes the first decoder to process an instruction to be processed when the instruction to be processed is a specific instruction and there is no previous instruction being processed, and causes the second decoder to process the instruction to be processed when the instruction to be processed is not the specific instruction or there is a previous instruction being processed.