Dual Insulating Layer Metal Line Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased aspect ratios of gaps between metal lines, causing gap-fill problems during metal deposition, particularly with conventional physical vapor deposition (PVD) processes, resulting in high electric resistivity and reliability issues.
Innovation Solution
A dual insulating layer method is employed, where a first insulating layer is patterned on a semiconductor substrate, followed by metal deposition and planarization, and then a second insulating layer is formed to reduce the aspect ratio of gaps, allowing for effective metal line formation without voids using PVD sputtering and high-density plasma CVD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional PVD sputtering process is used for metal deposition, then metal lines can be formed, but gap-fill problems occur due to high aspect ratio of gaps
Solution Approach 1:
The insulating layer is divided into multiple segments (first insulating layer patterns) that are spaced apart, creating multiple smaller gaps with lower aspect ratios instead of one large gap. This segmentation allows conventional PVD sputtering to effectively fill the gaps without void formation.
Solution Approach 2:
The invention transitions from a single-layer insulating structure to a multi-layer dual insulating layer structure. By adding vertical dimensionality with the second insulating layer filled between metal lines, the effective gap aspect ratio is reduced, enabling reliable metal deposition.
2Productivity
If gap width and height are reduced for miniaturization, then device integration increases, but aspect ratio of gaps increases causing gap-fill difficulties
Solution Approach 1:
The continuous insulating layer is segmented into first insulating layer patterns with spaces between them. This segmentation reduces the effective gap dimensions that metal must traverse, lowering the aspect ratio and making gap-fill manufacturing easier despite continued device miniaturization.
Solution Approach 2:
The structure employs nested layers where the second insulating layer is positioned between and around the metal lines, effectively nesting the insulation within the metal interconnect structure. This nested arrangement reduces the vertical gap distance metal must fill.
3Ease of manufacture
If dual insulating layer method is used to reduce gap aspect ratio, then metal deposition becomes easier, but process complexity increases
Solution Approach 1:
The first insulating layer patterns are formed in advance before metal deposition, pre-configuring the gap structure to have reduced aspect ratios. This preliminary structuring enables subsequent metal deposition to proceed easily using conventional PVD sputtering without requiring complex in-situ gap modification techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables easy metal deposition and reduces electric resistivity by minimizing gap aspect ratios, avoiding the gap-fill issues and reliability problems associated with conventional methods, while maintaining low electric resistivity.
Implementation Method 1
The aluminum metal line is generally formed by a physical vapor deposition (PVD) process, also known as a sputtering process
Implementation Method 2
Another approach is to employ an aluminum gap-fill process using chemical vapor deposition (CVD)
Data Source
AI summary
A method for forming a plurality of metal lines in a semiconductor device including forming first insulating layer patterns on a semiconductor substrate, the first insulating patterns being spaced from each other; depositing a metal layer on and between the first insulating layer patterns; planarizing the metal layer; patterning the planarized metal layer to form the plurality of metal lines between the first insulating layer patterns; and forming a second insulating layer on and between the metal lines.