Dual-Interface Memory Card Segmentation for High-Speed Data Transfer
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Solution Overview
Problem
The existing data transfer systems using PCIe for memory cards face issues with decreased transfer speed and increased costs due to complex configurations and the need for multiple control components, particularly when integrating two communication paths for high-speed and standard data communication.
Innovation Solution
The proposed solution involves a memory card with two external interfaces, a first interface unit for high-speed data communication and a second interface unit for standard data communication, connected to a system host via an adapter with a protocol converter, reducing the number of control components and enabling efficient communication by associating identifiers between the memory unit and additional information registration unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a daisy chain connection is made between external devices with physically different external interfaces, then interface compatibility is improved, but transfer performance for switching is degraded and cost increases due to complicated configuration
Solution Approach 1:
The external device is divided into two independent interface units: a first interface unit for high-speed data transfer and a second interface unit for standard control commands. This segmentation allows each interface to operate independently without switching overhead, resolving the contradiction by maintaining high transfer performance while supporting multiple interface types through the first interface unit's ability to handle different physical signals
Solution Approach 2:
The first interface unit is designed with multi-functionality to support multiple types of physical signals and communication protocols. This universal interface can adapt to different external interfaces (e.g., USB 3.1, Thunderbolt) while maintaining high-speed data transfer capability, thus achieving interface compatibility without degrading transfer performance or requiring complex switching components
2Adaptability or versatility
If a chip that integrates two communication paths is used, then interface compatibility is improved, but device complexity and cost increase
Solution Approach 1:
Instead of using an integrated chip that combines multiple communication paths, the invention segments the functionality into separate interface units. The first interface unit handles high-speed data transfer independently, while the second interface unit handles control commands independently. This eliminates the need for complex integrated switching chips and reduces device complexity while maintaining interface compatibility
Solution Approach 2:
The system introduces an intermediary mechanism in the form of identifier-based association between the first and second interface units. Rather than using a complex integrated chip to manage multiple communication paths, simple identifier matching serves as the mediator to link the two independent interface units, significantly reducing configuration complexity
3Reliability
If multiple control components are used for data transfer, then communication reliability is improved, but transfer speed decreases
Solution Approach 1:
The communication function is segmented into two independent paths: a first interface unit dedicated to high-speed data transfer and a second interface unit dedicated to reliable control command transmission. By separating control functions from data transfer functions, the system achieves both high speed (through the first interface) and high reliability (through the second interface's dedicated control path) without the speed penalty of multiple control components in series
Solution Approach 2:
Identifier-based association acts as an intermediary mechanism that links the first and second interface units without requiring multiple control components in the data path. The identifier matching process occurs outside the critical data transfer path, allowing reliable association between interfaces while maintaining high transfer speed through the dedicated first interface unit
Data Source
AI summary
A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.