Dual-Interface Memory Testing via PCIe Init and SD Pin Signaling
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Solution Overview
Problem
Existing test systems and methods for high-speed memory devices, such as those with dual SD and PCIe interfaces, are not suitable, making testing inconvenient and complex.
Innovation Solution
A memory device with dual interface that includes a test method and system, utilizing a PCIe mode initialization procedure with voltage level switching on SD mode pins, and a status display circuit with a light-emitting diode to indicate test results, simplifying the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex test system is constructed to satisfy the hardware specification of high-speed memory devices, then testing capability is improved, but device complexity and ease of operation deteriorate
Solution Approach 1:
The memory device itself is designed to perform testing functions by utilizing its dual interface capability. The device can operate in either SD mode or PCIe mode, allowing it to serve both as the object under test and as the testing instrument, thereby eliminating the need for a separate complex test system.
Solution Approach 2:
The memory device performs self-testing by executing initialization procedures in PCIe mode that control voltage levels on SD mode pins. The device monitors its own operational status and generates test results internally, reducing dependency on external testing equipment.
2Reliability
If a complex test system is constructed to satisfy the hardware specification of high-speed memory devices, then testing capability is improved, but ease of operation deteriorates
Solution Approach 1:
The memory device leverages its dual interface design to perform testing operations directly. By switching between SD and PCIe modes, the device can execute comprehensive tests without requiring external specialized equipment, making the testing process more convenient and accessible.
Solution Approach 2:
The device autonomously executes initialization procedures, controls voltage switching, and generates test results. This self-service capability eliminates the need for operators to manage complex external test systems, significantly improving ease of operation.
3Measurement precision
If voltage level switching is performed during initialization procedure, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The memory device dynamically switches between SD and PCIe modes during the initialization procedure. This dynamic mode switching enables precise control of voltage levels on different pins at different stages of initialization, improving measurement precision without requiring permanent complex circuitry.
Solution Approach 2:
The device changes operational parameters by transitioning between SD and PCIe modes. This parameter change approach allows flexible control of voltage levels and signal characteristics during testing, achieving high measurement precision through software-controlled mode transitions rather than complex hardware circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Facilitates quick and accurate testing of high-speed memory devices by reducing system complexity and enhancing testing convenience through real-time status and result display.
Implementation Method 1
a status display circuit with a light-emitting diode to indicate test results
Data Source
AI summary
Disclosed is a memory device with dual interface, test method and test system thereof. An initialization procedure is executed by the memory device with dual interface in a PCIe mode. A voltage level of a pin of the memory device with dual interface is altered according to the initialization procedure, wherein the pin of the memory device with dual interface operates in a SD mode but not in PCIe mode. The voltage level of the pin of the memory device with dual interface is switched between a high voltage level and a low voltage level at a first frequency during a test stage of the initialization procedure. The voltage level of the pin of the memory device with dual interface is kept at the high voltage level or the low voltage level during a result display stage of the initialization procedure.