Dual-Interface Storage Device Parallel Data Transfer
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Solution Overview
Problem
Current information storing devices using nonvolatile semiconductor memory devices face limitations in speed and capacity due to the reliance on mechanical components and single-memory-unit architectures, which hinder efficient data transfer and storage operations.
Innovation Solution
The implementation of a dual-interface information storing device with separate memory units and controllers, each communicating with the host via distinct interfaces, allows for parallel data operations and improved speed, while also utilizing a layered or stacked interface configuration on a printed circuit board to reduce size and enhance thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single memory unit and controller architecture is used, then the device complexity is low, but the data transfer speed and operational efficiency are limited
Solution Approach 1:
The storage device is divided into multiple independent memory units (first memory unit, second memory unit, etc.), each with its own controller and interface. This segmentation allows parallel data operations across multiple units, significantly increasing data transfer speed while distributing the overall system complexity across modular components rather than concentrating it in a single complex unit.
Solution Approach 2:
Each memory unit is designed with universal functionality to communicate with the host through its own interface, allowing any memory unit to handle data operations independently. This multi-functional design enables parallel processing capabilities where multiple units can simultaneously perform read, write, or erase operations, enhancing speed without requiring a completely different architecture for each unit.
2Productivity
If multiple memory units with separate interfaces are implemented, then parallel data operations and speed are improved, but the device size and manufacturing complexity increase
Solution Approach 1:
By segmenting the storage device into standardized memory units with identical internal architectures (controller, buffer memory, nonvolatile memory), each unit can be manufactured independently using the same processes. This modular segmentation allows for streamlined manufacturing where proven designs can be replicated across multiple units, reducing overall manufacturing complexity despite the increased number of components.
Solution Approach 2:
Each memory unit integrates multiple functional components (controller, buffer memory, nonvolatile memory) into a single packaged unit. This merging of components within each module simplifies the overall system assembly and manufacturing, as pre-integrated units can be directly mounted on the printed circuit board rather than assembling individual components, thereby improving ease of manufacture.
3Volume of moving object
If memory units are mounted on opposite surfaces of the printed circuit board, then the device size is reduced, but the interface configuration and assembly complexity increase
Solution Approach 1:
The memory units are arranged in a three-dimensional configuration by mounting them on opposite surfaces of the printed circuit board. This utilization of the Z-dimension (vertical stacking) rather than only the X-Y plane allows significant reduction in the device's footprint while maintaining all necessary interface connections through appropriate routing on both sides of the board.
Solution Approach 2:
By placing different memory units on opposite surfaces of the printed circuit board, the interface connections are segmented and distributed across both sides of the board. This segmentation of the interface configuration allows for organized, manageable routing schemes where each surface handles its own set of interfaces, reducing the overall complexity compared to trying to connect all units from a single side.
Data Source
AI summary
Disclosed is an information storing device which includes a first interface for connection with a host; a second interface for connection with the host; a first memory unit including a first controller controlling a first nonvolatile memory, the first controller communicating with the host via the first interface; and a second memory unit including a second controller controlling a second nonvolatile memory, the second controller communicating with the host via the second interface.