Dual-Interposer IC Package Without Back-Side Interconnects
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Solution Overview
Problem
Existing semiconductor packaging techniques face challenges in achieving high integration density and thermal management while maintaining flexibility in circuit design, particularly due to reliance on back-side interconnect structures and super power rails.
Innovation Solution
The integration of a first interposer in physical and electrical contact with the backside interconnect structures of integrated circuit dies and a second interposer coupled with the front-side interconnect structures, allowing for hybrid bonding that reduces thermal resistance and enhances circuit design flexibility without relying on back-side interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If back-side interconnect structures and super power rails are used, then electrical connectivity is achieved, but thermal resistance increases and circuit design flexibility is reduced
Solution Approach 1:
The patent transitions from two-dimensional planar interconnect structures on the backside to three-dimensional vertical interposer structures that extend through the package. Through-silicon vias and stacked interconnect layers enable electrical connectivity in the vertical dimension, reducing thermal resistance by providing direct thermal pathways while maintaining electrical functionality.
Solution Approach 2:
The patent introduces interposers as intermediary components between the substrate and overmolded semiconductor devices. These interposers serve as mediators that provide both electrical connectivity through controlled impedance traces and thermal management through dedicated thermal vias and heat dissipation structures, eliminating the need for back-side interconnect structures on the devices themselves.
2Reliability
If back-side interconnect structures are used, then electrical connectivity is achieved, but circuit design flexibility is reduced
Solution Approach 1:
The patent segments the interconnect function into separate components: substrate traces, interposer traces, and device pads. This segmentation allows independent optimization of each component for its specific function, enabling greater circuit design flexibility as designers can configure interposer trace routes and impedance matching independently of device backside interconnect constraints.
Solution Approach 2:
The interposer serves multiple functions simultaneously: electrical connectivity, signal routing, impedance matching, and thermal management. This multi-functionality eliminates the need for specialized back-side interconnect structures, providing circuit design flexibility as the same interposer infrastructure supports various device types and configurations.
3Reliability
If integrated circuit dies are packaged with traditional techniques, then device protection is achieved, but thermal management performance is reduced
Solution Approach 1:
The patent implements a nested packaging structure where the overmold encapsulates the semiconductor device and interposer assembly, providing mechanical protection and environmental sealing. Within this nested configuration, thermal management pathways are integrated through the interposer and substrate layers, allowing simultaneous achievement of device protection and effective heat dissipation.
Solution Approach 2:
The interposer acts as an intermediary thermal management component between the high-power semiconductor die and the external environment. Thermal vias and heat spreader structures within the interposer create efficient thermal pathways that conduct heat away from the device while the overmold provides protective encapsulation, resolving the contradiction between protection and thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves thermal management and circuit design flexibility by reducing thermal resistance and eliminating the need for back-side interconnect structures, thereby enhancing the performance of integrated circuit packages.
Implementation Method 1
hybrid bonding that reduces thermal resistance
Data Source
AI summary
A package includes an encapsulant having a first side and a second side opposite to the first side, a first integrated circuit die and a second integrated circuit die embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package further includes a second interposer on the second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die.