Dual I/O Line Pairs for High Data Rate Memory
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Solution Overview
Problem
Conventional DRAM architectures face challenges in achieving high data transfer rates without increasing burst length or memory core speed, particularly in realizing a 16 times data rate with a prefetch size of 16n, which is incompatible with typical cache line sizes and circuit structures.
Innovation Solution
The semiconductor device employs dual I/O line pairs, allowing for concurrent operation of local and main I/O lines to achieve 2n times data output rates per column cycle, enabling a 16n data rate with an 8n prefetch size every half-column cycle, without increasing burst length or core speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prefetch size is increased to 16n to achieve 16 times data rate, then data transfer rate is improved, but burst length becomes incompatible with typical cache line size of 64 bytes
Solution Approach 1:
The patent divides the data transfer path into two separate I/O line pairs (first and second common data I/O line pairs), each handling 8n prefetch data independently. This segmentation allows the system to maintain 8n prefetch size (compatible with 64-byte cache lines) while achieving 16n effective data rate through parallel operation of the two I/O line pairs.
2Productivity
If prefetch size is increased to 16n to achieve 16 times data rate, then data transfer rate is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the memory array into two banks, each connected to a separate I/O line pair, allowing independent access. This enables the use of conventional 8n prefetch circuitry in each bank rather than requiring complex 16n prefetch circuits, thereby achieving high data rates while maintaining manageable circuit complexity.
Solution Approach 2:
The patent combines the output data from two separate 8n prefetch operations (from first and second I/O line pairs) to achieve an effective 16n data rate. By merging the data streams from two simpler circuits rather than using one complex circuit, the system achieves high performance with reduced individual circuit complexity.
3Productivity
If core speed is doubled to achieve 16 times data rate with 8n prefetch, then data transfer rate is improved, but timing challenges and circuit complexity increase
Solution Approach 1:
The patent employs periodic alternating operation of the two I/O line pairs, where one pair is active during a first time period and the other pair is active during a second time period. This periodic switching allows the system to maintain a steady high data rate output while each individual circuit operates at the original clock speed, avoiding the timing challenges of doubled core speed.
Data Source
AI summary
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.