Dual-Issue Multiply Pipeline for DSP Throughput and Memory Bandwidth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns and simultaneous handling of multiple data streams.
Innovation Solution
The implementation of a dual-issue multiply instruction method using two multiplication units within a processor's data path, allowing for simultaneous multiplication and storage of operands, along with an autonomous streaming engine that manages data streams and improves memory bandwidth by bypassing lower-level caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single multiplication unit is used in the processor data path, then the device complexity is reduced, but the processing speed and productivity are limited due to sequential operation
Solution Approach 1:
The multiplication function is segmented into two separate multiplication units (first multiplication unit and second multiplication unit) that operate independently in parallel. Each unit handles a separate multiplication operation simultaneously, effectively doubling the throughput of multiply operations without requiring a single complex multi-functional unit.
Solution Approach 2:
Two multiplication units are merged into a single data path architecture, allowing both units to be controlled by a single dual-issue multiply instruction. The units share common control logic and can write results to the same or different destination locations, combining the benefits of parallel processing with unified control.
2Productivity
If memory bandwidth is limited, then the device complexity is reduced, but the processing efficiency deteriorates due to cache miss stalls
Solution Approach 1:
The autonomous streaming engine performs preliminary actions by pre-fetching and buffering data from memory before the main processor needs it. The streaming engine can independently manage data streams, performing address generation and data loading in advance, so that when the processor executes multiply instructions, the data is already available in buffers, eliminating cache miss stalls.
3Productivity
If a single issue instruction architecture is used, then the device complexity is reduced, but the productivity is limited due to sequential instruction execution
Solution Approach 1:
The instruction architecture is made dynamic by implementing dual-issue capability that can adaptively issue two multiply instructions per cycle when the instruction stream and resource availability permit. The control logic dynamically determines whether to issue one or two instructions based on operand readiness and destination availability, optimizing throughput without requiring a completely static complex architecture.
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.