Dual-Issue Multiply Architecture for Real-Time Data Scheduling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to memory bandwidth and scheduling constraints, particularly in applications requiring predictable but non-sequential input data patterns.
Innovation Solution
A dual-issue multiply instruction processor architecture is implemented, featuring two multiplication units with multiplexing logic and carry-save adder circuitry, along with a streaming engine that manages multiple data streams, enhancing memory bandwidth and data scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple multiplication units are used to increase processing throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple multiplication units into a single integrated structure where first and second multiplication units share common resources including multiplexing logic, carry-save adder circuitry, and output routing. This merging approach increases processing throughput by enabling parallel multiplication operations while reducing device complexity by eliminating redundant components through resource sharing.
Solution Approach 2:
The multiplication units are designed with universal components that serve multiple functions: the multiplexing logic selectively routes outputs from either multiplication unit to common adder circuitry, and the carry-save adder structure handles both partial sum and partial carry generation for multiple input sources. This multi-functionality enables increased productivity without proportional increases in device complexity.
2Speed
If carry-save adder circuitry is used to reduce critical path delay, then speed is improved, but device complexity increases
Solution Approach 1:
The addition operation is segmented into two independent stages: carry-save addition that generates partial sum and partial carry without resolving carries, followed by a final carry-propagate addition. This segmentation reduces critical path delay by avoiding long carry chains in the main computation path, while the modular carry-save structure keeps device complexity manageable through systematic decomposition of the addition function.
Data Source
AI summary
Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.