Dual Issue Queue Out-of-Order Execution for Energy Efficiency
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Solution Overview
Problem
Existing data processing systems that execute instructions out-of-order face challenges in managing dependencies, leading to high costs and energy consumption due to the need for extensive out-of-order hardware components, as many instructions ultimately execute in order and do not benefit from reordering.
Innovation Solution
A data processing apparatus that divides instructions into two subsets, where one subset is executed out-of-order using out-of-order components to remove false dependencies, and the other subset is constrained to execute in order, reducing the need for extensive out-of-order hardware by using a dual issue queue system and dependency management circuitry to handle true and false dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If out-of-order hardware components are used to execute instructions out of order, then instruction execution flexibility and performance are improved, but device complexity and energy consumption increase significantly
Solution Approach 1:
The patent segments the instruction stream into two subsets: instructions that can execute in-order and instructions that require out-of-order execution. This segmentation allows the system to apply complex out-of-order handling only where necessary, reducing overall hardware complexity while maintaining performance benefits for critical instructions.
Solution Approach 2:
The patent applies different execution qualities to different instruction subsets: in-order execution for simple instructions and out-of-order execution for instructions requiring flexibility. This local differentiation optimizes resource usage by avoiding uniform application of complex out-of-order hardware to all instructions.
2Productivity
If the size of out-of-order hardware components is increased to improve performance, then the instruction window size increases, but energy consumption and cost increase
Solution Approach 1:
The patent divides instructions into two subsets with different execution requirements, allowing the system to maintain a smaller out-of-order hardware footprint while still providing adequate instruction window capacity for instructions that truly benefit from out-of-order execution.
Solution Approach 2:
The patent applies out-of-order execution capability partially, only to the subset of instructions that require it, rather than providing full out-of-order capability for all instructions. This partial application reduces hardware size and energy consumption while maintaining sufficient performance.
3Adaptability or versatility
If all instructions are processed through out-of-order components, then execution flexibility is maximized, but energy is wasted on instructions that execute in order anyway
Solution Approach 1:
The patent segments instructions into those that benefit from out-of-order execution and those that do not, allowing the system to bypass complex out-of-order components for instructions that will execute in-order anyway, thereby eliminating energy waste while preserving execution flexibility where needed.
Solution Approach 2:
The patent enables instructions to self-identify their execution requirements through the in-order/out-of-order detector, allowing the system to automatically route instructions appropriately without wasting energy on unnecessary out-of-order processing for in-order instructions.
4Productivity
If a single large issue queue is used to manage all instructions, then instruction window capacity is maximized, but device complexity and cost increase
Solution Approach 1:
The patent divides the issue queue into two separate queues: one for in-order instructions and one for out-of-order instructions. This segmentation reduces the complexity of each individual queue while maintaining the total instruction window capacity, as each queue can be optimized for its specific instruction type.
Solution Approach 2:
The patent applies different queue management characteristics to different instruction subsets, with the in-order queue using simpler management and the out-of-order queue using more complex management only where necessary. This local differentiation reduces overall device complexity while maintaining capacity.
Data Source
AI summary
A data processing apparatus and method are provided for executing a stream of instructions out-of-order with respect to original program order. At least some of the instructions in the stream identify one or more architectural registers from a set of architectural registers. The apparatus comprises a plurality of out-of-order components configured to manage execution of a first subset of instructions out-of-order, the plurality of out-of-order components being configured to remove false dependencies between instructions in the first subset. The plurality of out-of-order components include a first issue queue into which the instructions in the first subset are buffered prior to execution. A second issue queue is used to buffer a second subset of instructions prior to execution, the second subset of instructions being constrained to execute in order. Issue control circuitry is configured to reference both issue queues in order to determine an order of execution of instructions, and is configured to constrain the order of execution of the first subset of instructions by true dependencies between the instructions in both the first and second issue queues, and to constrain the order of execution of the second subset of instructions by both the true dependencies and the false dependencies between the instructions in both the first and second issue queues. This approach provides improved performance and/or reduced energy consumption.