Dual L2 Cache Directory Structure for Multiprocessor Coherence
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Solution Overview
Problem
In large shared-memory multiprocessor systems, maintaining cache coherence across multiple processors with a single inclusive L2 system cache becomes impractical due to the large size requirements, leading to inefficiencies and complexities in managing data and coherency.
Innovation Solution
Implementing a dual L2 system cache directory structure with a superset cache directory for data and a subset cache directory for coherency, both equally sized and accessible to all processors, where only the superset directory hosts recent data, simplifying cache hit evaluations and reducing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single inclusive L2 system cache directory is used to manage cache coherence in large shared-memory multiprocessor systems, then cache coherence can be maintained, but the size of the L2 system cache memory becomes too large to be practical
Solution Approach 1:
The patent divides the L2 system cache directory into two separate directories: a data directory that stores actual cache data and a coherency directory that stores only coherency information (processor ID, address, state). This segmentation allows the system to maintain comprehensive coherency tracking without requiring all processors to have full L1 cache contents stored in the L2 cache memory, thus resolving the contradiction between maintaining cache coherence and limiting L2 cache size.
2Device complexity
If a single L2 system cache directory is used, then coherency management is simplified, but additional logic is required to evaluate which entries have data and which do not
Solution Approach 1:
By separating the data directory from the coherency directory, the patent enables independent optimization of each directory's function. The coherency directory can be searched efficiently for coherency status without needing to evaluate data presence, while the data directory only needs to store actual data entries. This segmentation simplifies the overall operation by eliminating the need for complex evaluation logic to determine data presence.
3Quantity of substance
If the combined size of processor L1 cache memories is large, then more data can be cached at processor level, but the L2 system cache memory size required becomes impractically large
Solution Approach 1:
The patent extracts the coherency management function from the data storage function by creating a separate coherency directory. This allows the L2 cache system to maintain coherency information for all processor L1 caches without storing the actual data in the L2 cache memory. The coherency directory only stores minimal metadata (processor ID, address, state), dramatically reducing the required L2 cache memory size while still supporting large processor-level caches.
Data Source
AI summary
A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.