Dual-Latch Flip-Flop Topology for Half-Clock Power Reduction
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Solution Overview
Problem
Integrated circuits with complex clock routing consume excessive power due to clock routing and capacitance, which is wasteful and counterproductive for low-power applications.
Innovation Solution
Implementing a dual latch flip flop device that operates at half the clock speed, using a pair of D latches with alternating enable signals to reduce clock frequency, thereby replacing conventional flip flops and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional flip flops are used with full clock speed, then circuit performance is maintained, but power consumption increases due to clock routing and capacitance
Solution Approach 1:
The circuit is segmented into two functional groups: sections operating at full clock speed and sections operating at half clock speed. Each section can be independently configured to use the appropriate clock frequency, allowing power optimization without compromising overall circuit performance. The dual latch flip flop device enables this segmentation by accepting either full-speed or half-speed clock signals.
Solution Approach 2:
The clock frequency parameter is changed from full speed to half speed for specific circuit sections where data activity is low. This parameter change reduces the switching activity and associated power consumption in those sections, while the dual latch flip flop maintains data integrity despite the reduced clock frequency.
2Loss of energy
If clock frequency is reduced to half speed, then power consumption decreases, but data throughput may be affected
Solution Approach 1:
Two latches are combined in a dual latch flip flop configuration where one latch captures data on the rising edge of the half-speed clock while the other latch captures data on the falling edge. This merging of two latches operating at half speed effectively provides full-speed data throughput capability while consuming less power than a single full-speed latch would require.
Solution Approach 2:
The half-speed clock signal creates periodic action with twice the period of the original full-speed clock. During each period, data is captured alternately by the two latches, ensuring that data throughput is maintained despite the reduced clock frequency. This periodic sampling approach allows power reduction while preserving functional performance.
Data Source
AI summary
An example device includes a first latch configured to receive data and a half-clock signal and a second latch in parallel with the first latch, The second latch is configured to receive the data and an inverted half-clock signal. The device further includes an output circuit connected to data outputs of the first and second latches. The output circuit provides the data alternately from the first latch and the second latch according to the half-clock signal. The device may be used in a processing element of a single instruction, multiple data (SIMD) computing device to save power.