Dual-Latch Page Buffer Circuit for Faster Read and Verify

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Solution Overview

Problem

Existing non-volatile memory devices face challenges in minimizing data sensing operations, leading to prolonged read and verify operation times.

Innovation Solution

A page buffer circuit with a data transfer circuit and dual latch circuits that sense and store data on multiple sensing nodes using distinct trip voltages, allowing simultaneous data sensing on both nodes, thereby reducing the number of operations required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a conventional single latch circuit is used for data sensing, then the circuit structure is simple, but the read and verify operation time is prolonged

Engineering Contradiction:

Improvecircuit structureVSAvoidread and verify operation time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent divides the sensing operation into two independent parallel paths: a first sensing node with a first latch circuit and a second sensing node with a second latch circuit. Each sensing node independently senses data from different bit lines simultaneously, eliminating the need for sequential sensing operations and thereby reducing total operation time despite increased circuit complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimension sensing approach (one sensing node at a time) to a multi-dimensional approach by introducing multiple sensing nodes (first sensing node and second sensing node) that operate in parallel. This dimensional expansion allows simultaneous data sensing across multiple bit lines, significantly reducing read and verify operation times

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple sensing nodes are used for simultaneous data sensing, then the read and verify operation time is reduced, but the device complexity increases

Engineering Contradiction:

Improvedata sensing speedVSAvoidpage buffer circuit structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The page buffer circuit is segmented into independent sensing units, each consisting of a sensing node and its corresponding latch circuit. The first sensing node and second sensing node are independently configured with their own latch circuits, allowing parallel operation without requiring complex interconnections or coordination logic between sensing units

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The latch circuits are pre-configured to capture data at their respective sensing nodes simultaneously. The first latch circuit is prepared to sense data from the first bit line while the second latch circuit is prepared to sense data from the second bit line, enabling concurrent data capture without requiring complex timing control mechanisms

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12482504B2Page buffer circuit and operation method thereof

Publication Date: 2025.11.25 SK HYNIX INC

AI summary

A page buffer circuit may include: a data transfer circuit configured to transfer data, transferred to a first sensing node through a bit line, to a second sensing node during a data sensing operation; a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data; and a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data.