Dual Latch Page Buffer for Nonvolatile Memory Programming
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Solution Overview
Problem
Nonvolatile memory devices face inefficiencies in programming operations due to the need for dumping operations, which can slow down the process and reduce performance.
Innovation Solution
A nonvolatile memory device design that includes a page buffer with a first latch for bit line setup information and a second latch for forcing information, allowing independent output to a sensing node, eliminating the need for dumping operations during forcing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional page buffer structure with single latch is used, then the device complexity is reduced, but the programming speed and efficiency deteriorate due to required dumping operations
Solution Approach 1:
The page buffer is segmented into two independent latches: a first latch for storing bit line setup information and a second latch for storing forcing information. This segmentation allows independent control and output of different information types, eliminating the need for dumping operations and improving programming speed.
Solution Approach 2:
The patent introduces a dual-path output structure where the first latch connects to the sensing node through a first path and the second latch connects through a second path. This dimensional expansion from single-path to multi-path architecture enables parallel operation and eliminates sequential dumping requirements.
2Productivity
If dumping operations are performed during programming, then the page buffer can maintain simpler structure, but the operational time and productivity are reduced
Solution Approach 1:
The forcing information is prepared in advance in the second latch during the programming operation setup phase. This preliminary preparation eliminates the need for time-consuming dumping operations later, as the forcing information is already available in the correct latch for immediate use during forcing operations.
Solution Approach 2:
The dual latch structure enables continuous programming operations without interruption for dumping. The first latch handles bit line setup information while the second latch simultaneously holds forcing information, allowing the programming process to proceed continuously without stopping for data transfer operations.
3Adaptability or versatility
If independent latch structure with dual paths is implemented, then the programming operation flexibility is improved, but the device complexity increases
Solution Approach 1:
The dual latch structure provides universal functionality for different programming modes. The first latch handles standard programming operations while the second latch handles forcing operations, allowing the same page buffer structure to adapt to various programming requirements without needing separate dedicated circuits for each mode.
Data Source
AI summary
A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.