Dual-Latch Timing Scheme for Soft Error Detection
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Solution Overview
Problem
Modern integrated circuit data processing devices are increasingly susceptible to soft errors due to reduced capacitance and operating voltage, leading to higher incidence of errors as chip technology advances, making existing error correction methods impractical for large computational logic blocks.
Innovation Solution
A storage element, such as a latch, is designed to detect soft errors by using multiple latches that receive a common clock signal, with varying data path delays to set up and hold times, allowing for the detection of transient interference and providing a signal indicative of errors without requiring precise regulation of multiple clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes and associated circuitry are used to detect and correct soft errors, then soft error detection capability is improved, but device complexity and power dissipation increase significantly
Solution Approach 1:
The error detection function is segmented and distributed to individual latch elements rather than using a centralized error correction code system. Each latch independently detects errors in its own data path, eliminating the need for complex global error correction circuitry while maintaining detection capability across the entire computational block.
Solution Approach 2:
Each latch element performs self-diagnosis by monitoring its own data path for transient errors. The latch uses its internal circuitry to detect soft errors without requiring external error correction codes or additional dedicated error detection circuitry, thereby reducing overall system complexity.
2Measurement precision
If multiple clock signals with precisely regulated delays are used to detect transient errors, then error detection precision is improved, but device complexity and difficulty of operation increase
Solution Approach 1:
Multiple clock signals are merged into a single external clock signal that controls all latch elements. The precise timing relationships previously requiring multiple regulated clock signals are achieved instead through the inherent propagation delay differences of data paths within each latch, eliminating the complexity of multi-clock signal regulation.
Solution Approach 2:
Each latch element automatically establishes its own setup and hold times through its internal data path delay characteristics, rather than requiring external precise clock regulation. The latch self-adjusts its timing parameters based on its own circuit properties, simplifying operation.
3Device complexity
If a single external clock signal with adjusted setup and hold times is used, then device complexity is reduced, but transient error detection capability may be compromised
Solution Approach 1:
Each latch element is designed with locally optimized data path delay characteristics that are tailored to its specific function and position in the circuit. This local optimization ensures that each latch maintains adequate setup and hold times for reliable transient error detection, even though all latches share a common clock signal.
Solution Approach 2:
The setup and hold times of each latch are adjusted by modifying the delay parameters of its internal data path rather than by changing clock signal parameters. This allows each latch to be independently tuned for optimal error detection performance while using a single external clock signal.
Data Source
AI summary
A clock signal is received at a clock node of a latch module, and a data signal is received at a data node of the latch module. The data signal including information to be latched at a first latch of the latch module and at a second latch of the latch module. A first representation of the data signal to a first data node of the first latch is delayed relative to a second representation of the data signal to a corresponding first data node of the second latch to obtain a first timing requirement between the data signal and the clock signal relative to the first latch that is substantially different than a second timing requirement. An error signal is generated in response to different data being latched at the first latch than at the second latch.