Dual Layer Bus Architecture for SOC Bandwidth Management
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Solution Overview
Problem
Conventional SOC architectures face performance issues and high power consumption when processing multimedia data in MPEG formats due to overwhelming bandwidth demands, particularly during encoding and decoding processes.
Innovation Solution
A dual layer SOC bus architecture is introduced, featuring a main bus connecting critical modules to high-density main memory and a high-speed secondary bus connecting these modules to high-speed secondary memory, allowing bandwidth division and efficient data transfer between main and secondary memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional SOC architectures use a single bus to connect all modules to memory, then device complexity is reduced, but bandwidth capacity is insufficient for multimedia processing
Solution Approach 1:
The patent divides the single bus into two separate buses: a first bus for connecting processing modules to first memory, and a second bus for connecting processing modules to second memory. This segmentation allows independent data transfer paths, increasing overall bandwidth capacity without requiring a single complex high-capacity bus.
Solution Approach 2:
The patent introduces a second dimension to the memory architecture by adding another memory bank (second memory) accessible through a separate bus. This transforms the single-dimensional memory access pattern into a two-dimensional memory hierarchy, enabling parallel data retrieval and increasing effective bandwidth.
2Ease of manufacture
If conventional SOC architectures use a single bus architecture, then manufacturing simplicity is maintained, but multimedia processing performance is insufficient
Solution Approach 1:
The bus architecture is segmented into two independent buses that can be manufactured and tested separately before integration. Each bus connects specific modules to corresponding memory banks, allowing modular fabrication processes that maintain ease of manufacture while achieving higher processing performance through parallel data paths.
3Device complexity
If data is transferred through a single bus during encoding/decoding, then bus architecture simplicity is maintained, but main system bus bandwidth is overwhelmed
Solution Approach 1:
The patent segments bandwidth demands by routing different data transfers through separate buses. The first bus handles transfers for the first memory while the second bus handles transfers for the second memory, preventing any single bus from being overwhelmed and reducing overall energy consumption associated with high-bandwidth single-bus transfers.
Data Source
AI summary
A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master module to a high density memory and a secondary memory operating independently of the main bus and adapted to connect the dual master module to a high-speed secondary memory.