Dual-Layer Channel Transistor for Lower Resistance Memory Cells
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Solution Overview
Problem
The size limitation of CMOS transistors restricts the improvement of memory cell density in memory devices, as they induce parasitic resistance and degrade channel mobility due to increased channel resistance.
Innovation Solution
The development of dual-layered channel transistors with semiconductor materials having different resistances, where a lower resistance first channel layer is embedded within a higher resistance second channel layer, reducing overall channel resistance and enhancing mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are used as select transistors in memory cells, then device functionality is achieved, but device density is limited due to parasitic resistance and degraded channel mobility
Solution Approach 1:
The channel is segmented into multiple sub-channels arranged in series, where each sub-channel has optimized dimensions and material properties. This segmentation allows the total channel resistance to be distributed across multiple smaller resistance components, reducing the parasitic resistance impact on overall device performance while maintaining the required select transistor functionality.
Solution Approach 2:
Different regions of the channel are assigned different material compositions and structural properties to optimize local electrical characteristics. Specifically, the channel includes regions with varying semiconductor material compositions that provide different carrier mobilities and resistance characteristics, allowing high-density integration while maintaining low parasitic resistance through localized property optimization.
2Productivity
If transistor size is reduced to increase areal density, then more transistors fit on the chip, but parasitic resistance increases and channel mobility degrades
Solution Approach 1:
The channel structure transitions from a two-dimensional planar configuration to a three-dimensional multi-subchannel architecture. By stacking multiple sub-channels vertically and connecting them in series, the invention achieves higher areal density while maintaining adequate channel dimensions for acceptable mobility through the vertical dimension.
Solution Approach 2:
The channel is constructed using composite semiconductor materials with different band structures and carrier effective masses. This composite material approach enables each sub-channel to contribute differently to the overall transport characteristics, allowing density improvement while compensating for mobility degradation through material property optimization.
Data Source
AI summary
A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.