Dual-Layer CMOS Logic Layout for Higher Density and Fewer Vias
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Solution Overview
Problem
Existing semiconductor devices face challenges with densely packed logic devices, where metal structures compete for space, increasing fabrication expense and failure risk, and integrating memory and combinatorial logic in a single layer complicates wiring and reduces device density.
Innovation Solution
A dual-layer semiconductor device design with complementary metal oxide (CMOS) logic layers, where memory state logic and combinatorial logic are stacked separately, allowing orthogonal or parallel arrangements, independent power supply, and reduced via counts through strategic via placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory state logic and combinatorial logic are integrated in a same level, then device functionality is achieved, but metal structures compete for available space increasing fabrication expense and failure risk
Solution Approach 1:
The patent divides the logic device into two separate layers: a first layer containing memory state logic devices and a second layer containing combinatorial logic devices. This segmentation eliminates the competition for metal structure space that occurs when both logic types are integrated in a single layer, thereby reducing fabrication expense and failure risk while maintaining complete device functionality.
Solution Approach 2:
The patent transitions from a two-dimensional single-layer integration to a three-dimensional stacked architecture. By stacking the combinatorial logic layer above the memory state logic layer, the design utilizes the vertical dimension to separate metal structure domains, eliminating spatial competition and simplifying fabrication.
2Quantity of substance
If logic devices are densely packed, then device density is improved, but metal structures contribute to fabrication expense and increase failure risk
Solution Approach 1:
By segmenting the logic devices into two separate layers, each layer can be independently optimized for its specific function. This segmentation allows dense packing within each layer while reducing the overall failure risk by isolating potential failure modes to specific layers rather than affecting the entire device.
Solution Approach 2:
The stacked three-dimensional architecture enables dense packing of logic devices vertically while separating the metal structure domains. This dimensional transition allows high device density to be achieved without proportionally increasing metal structure complexity and associated failure risks.
3Ease of manufacture
If metal structures are used for connections, then device functionality is achieved, but fabrication expense increases and failure risk increases
Solution Approach 1:
The patent segments the metal structure requirements into layer-specific interconnect systems. Each logic layer has its own dedicated metal interconnect structures, eliminating the need for complex multi-purpose metal routing that would be required for single-layer integration. This segmentation reduces both fabrication expense and failure risk.
4Device complexity
If single layer integration is used, then fabrication process is simpler, but wiring complexity increases and device density is reduced
Solution Approach 1:
The patent resolves the contradiction by moving to a three-dimensional stacked architecture. The separate fabrication of two simpler layers is offset by the efficiency gains from vertical stacking, which dramatically increases device density while keeping each layer's fabrication process relatively simple.
Solution Approach 2:
The patent implements a nested structure where the second logic layer is positioned above and integrated with the first logic layer. This nesting allows both layers to be fabricated using relatively simple processes while achieving high overall device density through vertical integration.
Data Source
AI summary
A semiconductor device includes a first logic layer including first complementary metal oxide (CMOS) logic devices. A second logic layer is stacked on the first logic layer and includes second CMOS logic devices. A placement of the second CMOS logic devices relative to the first CMOS logic devices increases device density and reduces via count.