Dual-Layer Isolation FET Structure for Lower Gate-Drain Capacitance
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Solution Overview
Problem
In advanced technology nodes, the increased gate-drain capacitance in nanostructure transistors due to larger metal gate endcaps and source/drain epitaxy sizes leads to higher effective capacitance between the gate metal and source/drain contact metals, affecting the performance and complexity of integrated circuits.
Innovation Solution
The introduction of dielectric structures between adjacent channel stacks and the replacement of gate metals with dielectric material, along with the use of a dielectric helmet structure above channel stacks, reduces the gate-to-source/drain capacitance by minimizing the area of gate metal facing source/drain contact metals, thereby improving transistor performance and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If larger metal gate endcaps and source/drain epitaxy sizes are used, then transistor drive current is improved, but gate-drain capacitance increases
Solution Approach 1:
The patent extracts and removes the metal gate material from the endcap region, replacing it with dielectric material. This extraction eliminates the capacitive coupling between the gate and source/drain contact metals in the endcap region, directly reducing gate-drain capacitance while preserving the beneficial drive current characteristics achieved through larger epitaxy sizes.
Solution Approach 2:
The patent introduces dielectric material as an intermediary between the gate structure and source/drain contact metals in the endcap region. This intermediary layer acts as an electrical insulator that reduces parasitic capacitance while allowing the underlying epitaxy structure to maintain its current-carrying capability.
2Productivity
If advanced technology node scaling is implemented, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct regions: a conventional gate region and an endcap region. The endcap region is specifically modified by removing metal and replacing it with dielectric material, while the main gate region retains its metal structure. This segmentation allows selective optimization of different regions to address capacitance issues without compromising overall device performance.
Solution Approach 2:
The patent applies different material properties to different spatial regions of the transistor. Specifically, dielectric material is applied locally to the endcap region to reduce capacitance, while metal material is retained in the main gate region for optimal electrical performance. This local differentiation of material quality enables targeted problem solving.
Data Source
AI summary
An integrated circuit includes a transistor including a plurality of stacked channels. A first dielectric wall structure is positioned on a first lateral side of the stacked channels. A second dielectric wall structure is positioned on a second lateral side of the stacked channels. A dielectric home structure is positioned above the top channel. A gate electrode includes a vertical column extending vertically between the second dielectric wall structure and the stacked channels. The gate electrode includes finger portions extending laterally from the vertical column between the stacked channels.