Dual-Layer FET Isolation Structure for Gate Overlap Control
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Solution Overview
Problem
The scaling down of integrated circuits increases complexity and gate-drain capacitance due to larger metal gate endcaps and increased source/drain epitaxy size, necessitating improved active area spacing and transistor scaling.
Innovation Solution
A dual-layer isolation structure is formed between adjacent stacks of semiconductor nanostructures, comprising a shell dielectric layer and a core dielectric layer, followed by etching processes to control gate metal overlap and enhance wafer yields and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down is implemented to increase functional density, then production efficiency increases and costs lower, but device complexity and gate-drain capacitance increase
Solution Approach 1:
The isolation structure is divided into two distinct layers: a first dielectric layer forming an isolation region and a second dielectric layer forming a trench isolation structure. This segmentation allows each layer to perform specific functions - the first layer provides basic isolation while the second layer controls gate metal overlap, thereby managing device complexity in scaled-down configurations
Solution Approach 2:
The patent introduces vertical dimensionality by forming the second dielectric layer above the first dielectric layer, creating a multi-level isolation structure. This vertical arrangement enables independent control of isolation regions and trench isolation structures, allowing precise control of gate metal overlap without increasing lateral device complexity
2Productivity
If scaling down is implemented to increase functional density, then production efficiency increases and costs lower, but gate-drain capacitance increases
Solution Approach 1:
The first dielectric layer acts as an intermediary between the semiconductor nanostructures and the second dielectric layer. It forms isolation regions that mediate the interaction between adjacent transistors, while the second dielectric layer provides additional isolation that prevents gate metal from overlapping with source/drain regions, thereby reducing gate-drain capacitance
Solution Approach 2:
By segmenting the isolation function into two separate dielectric layers with distinct roles, the patent achieves better control over capacitance effects. The first layer handles basic transistor isolation while the second layer specifically addresses gate metal overlap, allowing optimized capacitance control in scaled devices
3Productivity
If active area spacing is reduced to improve transistor scaling, then integrated circuit performance enhances, but manufacturing precision requirements increase
Solution Approach 1:
The isolation structure is segmented into two functional layers that can be formed using different deposition and etching processes. The first dielectric layer is deposited and patterned first, then the second dielectric layer is deposited and selectively removed to form trenches. This segmentation allows each step to be optimized independently, reducing the overall precision burden on any single manufacturing step
Solution Approach 2:
The first dielectric layer is formed in advance as a preliminary isolation structure before the second dielectric layer is deposited. This preliminary action establishes the basic isolation regions, and subsequent processing steps can then focus on refining the trench isolation structures without requiring perfect precision in all steps simultaneously
Data Source
AI summary
A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.