Dual-Layer Gate Electrode Oxidation for Leakage Reduction
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Solution Overview
Problem
In semiconductor devices, the overlap of impurity ion regions with the lower region of the gate electrode leads to current leakage, reducing the reliability of the transistor.
Innovation Solution
A gate electrode is formed using layers with different oxidation rates, where the lower layer oxidizes at a higher rate than the upper layer, preventing overlap with the impurity regions and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer gate electrode is formed using polysilicon, then the manufacturing process is simple, but the corners of the gate electrode become rounded and impurity regions overlap with the lower region of the gate electrode causing current leakage
Solution Approach 1:
The gate electrode is divided into two separate layers: a lower gate electrode layer and an upper gate electrode layer. This segmentation allows each layer to serve different functions - the lower layer provides structural support while the upper layer forms the functional gate, preventing impurity overlap and corner rounding issues that occur in single-layer structures
Solution Approach 2:
The patent uses a composite structure combining two different material layers for the gate electrode. The lower layer and upper layer have different properties that complement each other, with the lower layer providing structural integrity and the upper layer providing optimal electrical characteristics, thereby preventing both rounding and impurity leakage issues
2Strength
If heat treatment is performed to form oxide layer on the gate electrode, then the gate electrode surface is protected, but the lower region of the gate electrode still overlaps with impurity regions causing current leakage
Solution Approach 1:
By segmenting the gate electrode into lower and upper layers, the patent creates a structure where the upper layer is positioned higher than the lower layer. This vertical separation ensures that when oxide layer is formed on the gate electrode through heat treatment, the impurity regions do not overlap with the functional upper gate electrode layer, preventing current leakage while maintaining protective oxidation
3Ease of manufacture
If sidewalls are formed by etching nitride layer and oxide layer, then the transistor structure is completed, but the impurity regions have already overlapped with the gate electrode lower region causing reliability issues
Solution Approach 1:
The patent performs preliminary action by forming the two-layer gate electrode structure before subsequent processing steps. The lower and upper gate electrode layers are formed and positioned correctly before sidewall formation and final transistor completion, ensuring that impurity regions are properly contained and will not overlap with the functional gate structure during later manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the gate electrode remains isolated from the impurity regions, enhancing the reliability and performance of the semiconductor device by preventing current leakage.
Implementation Method 1
forming an oxide layer by performing a heat treatment on the substrate and the gate electrode
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode includes an upper layer and a lower layer stacked on the gate insulating layer. The oxide layer is formed on the gate electrode. The lower layer and the upper layer can have different oxidation rates. The sidewalls are formed on the oxide layer.