Dual-Layer HEMT Gate Passivation for Voltage Withstand
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Solution Overview
Problem
There is a need for improvement in the manufacturing processes and performance of High Electron Mobility Transistors (HEMTs), particularly in terms of passivation layers to enhance voltage withstand and reduce leakage currents.
Innovation Solution
A HEMT transistor design featuring a first semiconductor layer, a gate, and passivation layers made of specific dielectric materials, where the second passivation layer extends between the gate and the first passivation layer, but not on the sides of the gate, using materials like alumina, silicon nitride, or silicon dioxide, to improve insulation and reduce lateral leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single passivation layer is used to cover the gate and semiconductor layer, then the manufacturing process is simple, but the voltage withstand capability and leakage current control are insufficient
Solution Approach 1:
The single passivation layer is segmented into two distinct layers: a first passivation layer covering the semiconductor layer and gate sides, and a second passivation layer covering the gate top surface and peripheral portions. This segmentation allows each layer to be optimized for specific functions - the first layer provides baseline protection and the second layer enhances voltage withstand capability at critical areas, thereby resolving the contradiction between simplicity and reliability.
Solution Approach 2:
Different regions of the gate structure receive different passivation coverage: the gate top surface receives the second passivation layer for enhanced voltage withstand, while the gate sides are covered by the first passivation layer. This local differentiation allows optimal protection at each location without uniformly increasing complexity across the entire device.
2Reliability
If conventional passivation is applied uniformly, then manufacturing is easier, but lateral leakage currents are not sufficiently reduced
Solution Approach 1:
The passivation structure is segmented into two layers with different spatial extents. The first passivation layer covers the gate sides and semiconductor layer, while the second passivation layer covers the gate top and peripheral portions. This segmentation creates a more comprehensive coverage scheme that effectively blocks lateral leakage paths without requiring uniform thick passivation everywhere, thus improving leakage control with moderate complexity increase.
Solution Approach 2:
The passivation approach transitions from a single-layer two-dimensional coverage to a multi-layer three-dimensional configuration. The second passivation layer extends over the gate top surface and peripheral portions, adding vertical layering and lateral extension beyond what a single planar layer could achieve, thereby blocking leakage paths in multiple dimensions.
3Reliability
If the second passivation layer covers the entire gate structure including sides, then insulation is maximized, but manufacturing complexity and potential damage increase
Solution Approach 1:
The passivation coverage is segmented such that the second passivation layer is applied selectively to the gate top surface and peripheral portions, while the first passivation layer covers the gate sides. This segmentation allows the gate etching process to be performed without requiring complete removal of extensive passivation coverage, reducing etching damage and simplifying manufacturing while maintaining insulation performance through the combined two-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described design enhances the voltage withstand capability and reduces leakage currents, improving the overall performance and reliability of HEMT transistors for high-power applications.
Implementation Method 1
a second passivation layer made of a second dielectric material extends between said face of the gate and the first passivation layer
Implementation Method 2
the sides of the gate not being coated by said second passivation layer... reduces leakage currents
Data Source
Figure 1~2B
Figure 2C~2E
Figure 2F~3
AI summary
The present description relates to a HEMT transistor (11) comprising: - a first semiconductor layer (13); - a gate (15) disposed on a first face of the first semiconductor layer (13); and - a first passivation layer (17) of a first dielectric material extending over said first face of the first semiconductor layer, the sides of the gate (15) and at least a peripheral part of a face of the gate opposite the first semiconductor layer, in which a second passivation layer (25) of a second dielectric material extends between said face of the gate and the first passivation layer, the sides of the gate (15) not being coated by said second passivation layer (25).