Dual-Layer Inner Spacers for Low-Capacitance GAA Transistors
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Solution Overview
Problem
Existing methods for fabricating inner spacers in multi-gate transistors, such as gate-all-around (GAA) transistors, fail to adequately reduce parasitic capacitance without shortening the effective channel length, complicating the manufacturing process.
Innovation Solution
A method involving the formation of inner spacers with a dual-layer or multi-layer dielectric structure, using selective etching to maintain the effective channel length while reducing parasitic capacitance, by employing alternating deposition and etching processes to form dielectric layers on the sidewalls of the channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If existing methods are used to fabricate inner spacers, then the manufacturing process is simplified, but parasitic capacitance cannot be adequately reduced without shortening the effective channel length
Solution Approach 1:
The inner spacer is divided into multiple dielectric layers with different compositions and properties. The first dielectric layer provides etching resistance during gate removal, while the second dielectric layer reduces parasitic capacitance. This segmentation allows each layer to fulfill its specific function without compromising the other, resolving the contradiction between reducing parasitic capacitance and maintaining manufacturing simplicity.
Solution Approach 2:
The inner spacer employs a composite structure combining two different dielectric materials. The first dielectric layer (e.g., silicon nitride or silicon oxynitride) offers high etching resistance, while the second dielectric layer (e.g., silicon oxide or low-k material) provides low parasitic capacitance. This composite approach enables simultaneous achievement of etching protection and capacitance reduction without increasing overall process complexity.
2Reliability
If the effective channel length is maintained, then gate control is improved, but parasitic capacitance reduction becomes more difficult
Solution Approach 1:
Different regions of the inner spacer are assigned different dielectric materials with optimized properties. The first dielectric layer is positioned to provide etching resistance where needed during fabrication, while the second dielectric layer is positioned to minimize parasitic capacitance in the critical region between the gate and source/drain. This local optimization allows maintenance of effective channel length for gate control while simultaneously reducing parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance without shortening the channel length, improving the reliability and performance of GAA transistors by maintaining gate control and mitigating short-channel effects.
Implementation Method 1
employing alternating deposition and etching processes to form dielectric layers on the sidewalls of the channel layers
Implementation Method 2
selective etching to maintain the effective channel length while reducing parasitic capacitance
Data Source
AI summary
A method includes forming a structure including a stack of alternating channel layers and sacrificial layers, and a dummy gate structure over the stack, forming a source/drain recess in a source/drain region of the stack and adjacent to the dummy gate structure, selectively and partially recessing the sacrificial layers from the source/drain recess to form first recesses, depositing a first dielectric layer in the first recesses, partially recessing the first dielectric layer to form second recesses, forming a second dielectric layer in the second recesses, forming an epitaxial source/drain feature in the source/drain recess and over the second dielectric layer, and replacing the dummy gate structure and the sacrificial layers with a high-k metal gate stack.