Dual-Layer Metal Oxide Transistor Interface Defect Isolation
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Solution Overview
Problem
BCE-type oxide thin film transistors suffer from low mobility and stability due to defects at the interface between the metal oxide semiconductor and the gate insulating layer, leading to reduced carrier concentration and increased carrier trapping.
Innovation Solution
A metal oxide thin film transistor structure is developed with a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, where the first layer has a high carrier concentration and hall mobility, and the second layer has a higher band gap, both made of indium gallium zinc oxide, to reduce defects and enhance carrier injection and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer oxide semiconductor structure is used in BCE-type thin film transistors, then the device structure is simple, but carrier mobility and stability are low due to interface defects
Solution Approach 1:
The active layer is divided into two separate oxide semiconductor layers: a first oxide semiconductor layer in contact with the gate insulating layer, and a second oxide semiconductor layer forming the channel. This segmentation isolates the interface defects between the first layer and gate insulating layer from the channel region, allowing carriers to flow through the cleaner second layer with higher mobility and stability.
2Ease of manufacture
If interface defects between metal oxide semiconductor and gate insulating layer are present, then manufacturing is easier, but carrier concentration decreases and carrier trapping increases
Solution Approach 1:
The first oxide semiconductor layer acts as an intermediary between the gate insulating layer and the channel-forming second oxide semiconductor layer. This intermediary layer absorbs the harmful interface effects from the gate insulating layer, preventing direct interaction that would cause carrier trapping and reduce carrier concentration in the channel.
3Device complexity
If a single-layer structure is used, then device structure is simpler, but on-state current is reduced due to carrier trapping
Solution Approach 1:
By segmenting the active layer into two functional zones - the first layer for interface isolation and the second layer for carrier transport - the structure enables higher on-state current. The second layer, free from direct interface defects, maintains higher carrier concentration and reduces trapping, thereby increasing the current flowing through the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure improves carrier mobility, on-state current, and stability by minimizing defect capture and increasing carrier concentration in the channel, while also enhancing light and thermal stability.
Implementation Method 1
the first metal oxide semiconductor layer is used to isolate the second metal oxide semiconductor layer from the gate insulating layer, such that an actual channel of the metal oxide thin film transistor is located in the second metal oxide semiconductor layer
Implementation Method 2
Since the first metal oxide semiconductor layer and the second metal oxide semiconductor layer are both metal oxide semiconductor materials with similar material type, the number of defects at an interface between the second metal oxide semiconductor layer and the first metal oxide semiconductor layer is small
Data Source
AI summary
A metal oxide thin film transistor is provided and includes a gate, a gate insulating layer, an active layer and a source-drain metal layer stacked on a side of a backplane, the active layer and the gate are provided on both sides of the gate insulating layer, the source-drain metal layer is provided on a side of the active layer away from the backplane, the active layer includes: a first metal oxide semiconductor layer provided on a side of the gate insulating layer away from the gate; a second metal oxide semiconductor layer provided on a surface of the first metal oxide semiconductor layer away from the gate.