Semiconductor Packaging Shielding Layout for Edge-Coverage Uniformity
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Solution Overview
Problem
Existing semiconductor packaging structures face challenges with inhomogeneous magnetic field shielding layers due to uneven thickness and poor edge coverage, leading to inadequate electromagnetic interference shielding.
Innovation Solution
A dual-layer shielding structure is formed by a first shielding layer covering non-functional surfaces and sidewalls, followed by a second shielding layer that addresses uneven thickness and edge coverage issues, enhancing overall shielding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single magnetic field shielding layer is provided on semiconductor packaging structure, then electromagnetic shielding is implemented, but the shielding layer has inhomogeneous thickness and poor edge coverage
Solution Approach 1:
The shielding structure is divided into multiple independent shielding layers (first shielding layer, second shielding layer, third shielding layer) with different materials and functions. Each layer addresses specific shielding requirements, allowing optimized deposition parameters for each layer to achieve both uniform thickness and complete edge coverage.
Solution Approach 2:
The patent uses composite shielding layers with different materials (e.g., copper layer, aluminum layer, magnetic field shielding material) to achieve both electric field shielding and magnetic field shielding. The composite structure allows each material to contribute its strengths, resulting in homogeneous overall shielding performance with improved edge coverage.
2Object-affected harmful factors
If existing electromagnetic shielding solutions are used, then electromagnetic interference shielding is provided, but edge coverage is poor and thickness is uneven
Solution Approach 1:
A first shielding layer is deposited beforehand to serve as a base layer that pre-covers the substrate surface including edges. This preliminary action ensures that subsequent layers have a uniform foundation to build upon, improving overall edge coverage and thickness homogeneity.
Solution Approach 2:
The patent introduces multiple shielding layers in the vertical dimension, each with different materials and thicknesses. This multi-dimensional approach allows optimization of deposition parameters for each layer to achieve complete edge coverage that cannot be achieved with a single layer.
3Reliability
If a magnetic field shielding layer is formed by sputtering process, then shielding is achieved, but edges of semiconductor packaging structure are not covered and thickness is inhomogeneous
Solution Approach 1:
Different deposition parameters (power, time, distance, gas flow) are optimized for each shielding layer to achieve uniform thickness. The sputtering parameters are specifically adjusted for each layer material and position to ensure homogeneous thickness distribution across the entire substrate including edges.
Solution Approach 2:
The sputtering process uses dynamic parameter adjustment during deposition, including real-time monitoring and adjustment of deposition rate, substrate rotation speed, and target-to-substrate distance, to maintain uniform thickness distribution across the substrate surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-layer shielding structure provides comprehensive electromagnetic interference shielding, improving the stability and reliability of semiconductor packaging by ensuring complete coverage and uniform thickness.
Implementation Method 1
forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips; forming a second shielding layer on the first shielding layer
Data Source
AI summary
Packaging structure and fabrication method are provided. The method includes: providing semiconductor chips; providing soldering pads on the semiconductor chips, a metal bump on each soldering pad, and a first plastic encapsulation layer on functional surfaces of the semiconductor chips; providing a carrier plate; adhering the first plastic encapsulation layer on the functional surfaces of the semiconductor chips to the carrier plate; forming a first shielding layer covering non-functional surfaces and sidewalls of the semiconductor chips; forming a second shielding layer on the first shielding layer; forming a second plastic encapsulation layer on the second shielding layer and on the carrier plate between semiconductor chips; peeling off the carrier plate to form a pre-packaging plate; removing a portion of the first plastic encapsulation layer to expose the metal bumps; forming an external contact structure on the backside of the pre-packaging plate and connected to each metal bump.


