Dual Layer Passivation for Leakage Mitigation in Transistors
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Solution Overview
Problem
Semiconductor devices, particularly transistors, face issues with substrate leakage currents and surface states that degrade performance, and alignment problems due to lack of natural passivation and transparency to light used in fabrication, making high-speed device fabrication challenging and costly.
Innovation Solution
Implementing a dual layer passivation strategy using dielectric materials like Si3N4 and SiO2, applied before and after mesa formation, to mitigate substrate leakage and surface states, while using an optically opaque alignment mark to enhance alignment accuracy during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single passivation layer is applied to the semiconductor surface, then the manufacturing process is simple, but substrate leakage currents and surface states cannot be effectively mitigated
Solution Approach 1:
The passivation layer is divided into two distinct layers: a first passivation layer applied to the semiconductor surface, and a second passivation layer applied over the first layer after mesa formation. This segmentation allows each layer to perform specific functions - the first layer provides initial surface passivation, while the second layer provides additional protection and enables alignment mark formation, collectively mitigating substrate leakage currents more effectively than a single layer could achieve.
Solution Approach 2:
The solution transitions from a single-layer passivation approach to a dual-layer passivation structure, adding a dimensional aspect to the passivation system. The first passivation layer is applied before mesa formation, and the second passivation layer is applied after mesa formation, creating a time-sequential and structural dual-layer configuration that enhances leakage mitigation capability.
2Measurement precision
If the semiconductor material is transparent to alignment light wavelengths, then the material has desirable electrical properties, but alignment marks are difficult to resolve during fabrication
Solution Approach 1:
An optically opaque material is introduced as an intermediary substance applied to the alignment mark region on the second passivation layer. This intermediary material provides the necessary optical contrast for alignment mark detection during photolithography, while the underlying transparent semiconductor material retains its desirable electrical properties. The opaque material acts as a mediator that enables optical detection without compromising the semiconductor's electrical characteristics.
Solution Approach 2:
The optically opaque material is applied locally only to the alignment mark region rather than uniformly across the entire device structure. This localized application provides the necessary optical contrast precisely where needed for alignment, while leaving the rest of the transparent semiconductor structure intact to maintain its electrical properties. The local quality change enables alignment without globally affecting the material's transparency.
3Reliability
If conventional single-layer passivation is used, then manufacturing costs are low, but device performance is degraded by leakage currents
Solution Approach 1:
The first passivation layer is applied in advance to the semiconductor surface before mesa formation occurs. This preliminary passivation establishes a stable base layer that prevents surface degradation during subsequent processing steps. By performing this passivation action beforehand, the structure is better prepared to handle the mechanical and chemical processes of mesa formation, ultimately improving device performance while using standard manufacturing sequences.
Solution Approach 2:
The dual-layer passivation structure provides beforehand protection against substrate leakage currents and surface states. The first passivation layer cushions the semiconductor surface during processing, and the second passivation layer provides additional protective cushioning after mesa formation. This layered cushioning approach mitigates harmful effects before they can degrade device performance, using materials and processes compatible with existing manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces gate leakage current and improves device performance by stabilizing the semiconductor surface and facilitating precise alignment, thereby enhancing the fabrication of high-speed semiconductor devices without significant modifications to existing manufacturing processes or costs.
Implementation Method 1
semiconductor devices, especially transistors are often sensitive to leakage currents from conductor and interconnections into the semiconductor bulk or substrate, and/or to surface states that may upset the electrical potential in critical device regions
Data Source
AI summary
Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.