Dual-Layer Poly Silicon Cell Plate Electrode for Capacitance Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional trench capacitor semiconductor memory devices face challenges in achieving high integration and effective capacitance due to low impurity concentration in the cell plate electrode, leading to depletion regions and reduced capacitance, which is exacerbated by increased manufacturing complexity and leakage currents when attempting to enhance impurity concentration or electrode thickness.
Innovation Solution
A dual-layer cell plate electrode structure is implemented, with a first poly silicon film having a higher impurity concentration than the second poly silicon film, which is used to form the gate electrodes, preventing depletion and allowing for stable capacitance while maintaining sufficient film thickness for transistor operations, and enabling the formation of resistor elements with different resistances on a single substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the cell plate electrode is increased to prevent depletion layer formation, then the effective capacitance is improved, but the manufacturing complexity and leakage currents increase
Solution Approach 1:
The cell plate electrode is divided into two distinct layers: a first poly silicon film with high impurity concentration to prevent depletion layer formation and ensure stable capacitance, and a second poly silicon film with lower impurity concentration to reduce manufacturing complexity and leakage currents. This segmentation allows each layer to optimize for its specific function.
Solution Approach 2:
Different regions of the cell plate electrode are assigned different impurity concentrations tailored to their specific functional requirements. The first layer (contacting the dielectric film) has high impurity concentration for depletion prevention, while the second layer (forming gate electrodes) has lower impurity concentration for reduced complexity.
2Reliability
If the cell plate electrode is thinned to reduce depletion, then the capacitance is improved, but the film thickness becomes insufficient for gate electrode formation
Solution Approach 1:
The electrode structure is segmented into two layers with different thicknesses and impurity concentrations. The first poly silicon film is thinner with higher impurity concentration for capacitance stability, while the second poly silicon film is thicker with lower impurity concentration to provide sufficient thickness for gate electrode formation and transistor operations.
Solution Approach 2:
The impurity concentration and thickness parameters are optimized differently for each layer. The first layer has high impurity concentration and appropriate thickness for preventing depletion, while the second layer has lower impurity concentration and greater thickness for mechanical stability and gate functionality.
3Quantity of substance
If ion implantation energy is increased to introduce impurities into the cell plate electrode, then the impurity concentration is improved, but the leakage currents increase
Solution Approach 1:
The impurity introduction process is segmented into two stages with different energy levels. The first poly silicon film receives high energy ion implantation to achieve high impurity concentration for depletion prevention, while the second poly silicon film receives lower energy implantation to maintain lower impurity concentration and minimize leakage currents.
Solution Approach 2:
The ion implantation energy parameter is changed between the two layers. High energy is used for the first layer to achieve deep impurity penetration and high concentration, while lower energy is used for the second layer to achieve moderate concentration without excessive leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces depletion in the cell plate electrode, maintains stable capacitance, and allows for the fabrication of resistor elements with varying resistances without increasing the layout area, thereby improving device performance and manufacturing efficiency.
Implementation Method 1
an impurity concentration of the first poly silicon film in the trench of the cell plate electrode is higher than the impurity concentration of the second poly silicon film filled inside of trench of the cell plate electrode
Implementation Method 2
a second poly silicon film formed on the first poly silicon film to completely fill the trench; wherein the second poly silicon film includes a sufficient film thickness for forming the gate electrodes
Data Source
AI summary
A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.