Dual-Layer Sintered Silver Bonding for Crack-Resistant Power Packages

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Solution Overview

Problem

Existing pressureless silver sintering technologies face issues of cracking and delamination at critical interfaces in chip bonding, impacting the reliability of high-power semiconductor packages.

Innovation Solution

A dual-layer sintered silver bonding structure is employed, with a first layer having low porosity and uniform spherical particles, and a second layer with columnar or block-like particles and low Young's modulus, to buffer and resist shear forces caused by thermal expansion mismatches, preventing cracking and enhancing adhesion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If pressureless silver sintering technology is used for chip bonding, then thermal conductivity is improved, but cracking and delamination occur at critical interfaces

Engineering Contradiction:

Improvethermal conductivityVSAvoidinterface reliability

Core Design Contradiction:

TemperatureVSReliability

Solution Approach 1:

The bonding structure is segmented into a dual-layer silver sintering configuration: a first silver sintering layer bonded to the substrate and a second silver sintering layer bonded to the chip. This segmentation allows each layer to be optimized independently - the first layer for strong substrate adhesion and the second layer for chip bonding - thereby preventing cracking and delamination while maintaining thermal conductivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses composite silver sintering layers with different properties. The first silver sintering layer has optimized composition and structure for substrate adhesion, while the second layer is optimized for chip bonding. This composite approach allows simultaneous achievement of high thermal conductivity and interface reliability that a single-layer structure cannot provide.

Inventive Principle:

Principle #40Composite materials

2Ease of manufacture

If high-lead solder is used for bonding, then cost is reduced, but thermal conductivity is limited to approximately 45 W/m·K

Engineering Contradiction:

Improvebonding costVSAvoidthermal conductivity

Core Design Contradiction:

Ease of manufactureVSTemperature

Solution Approach 1:

The invention changes the material parameter from traditional high-lead solder to silver sintering paste, which has superior thermal conductivity properties. By optimizing the silver particle size distribution, sintering temperature, and paste composition, the bonding process achieves both cost-effectiveness and enhanced thermal performance exceeding 45 W/m·K.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If silver paste is applied at high temperature, then sintering is achieved, but lateral shear force from thermal expansion mismatch causes cracking

Engineering Contradiction:

Improvesintering temperatureVSAvoidbonding strength

Core Design Contradiction:

Use of energy by moving objectVSStrength

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the bonding structure are given different properties: the first silver sintering layer near the substrate is optimized for thermal stability and adhesion, while the second layer at the chip interface is optimized for bonding strength and flexibility. This local quality differentiation allows the structure to withstand thermal expansion mismatches without cracking.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dual-layer structure maintains high heat dissipation and reliability by resisting lateral and normal shear forces, reducing interface cracking, and ensuring the integrity of the power semiconductor package.

Implementation Method 1

A sintering process is performed on the first silver paste and the second silver paste to form a dual-layer sintered silver bonding structure

Methodology Applied

Scientific EffectSintering: Sintering

Implementation Method 2

The first sintered silver layer is configured to resist a lateral shear force generated by a mismatch in coefficients of thermal expansion between the epoxy molding compound and the substrate

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20260005182A1Power semiconductor package and fabrication method thereof

Publication Date: 2026.01.01 TONG HSING ELECTRONICS IND LTD

AI summary

A power semiconductor package includes a substrate; a chip affixed to the substrate via a dual-layer sintered silver bonding structure; and an epoxy molding compound that at least encapsulates the chip and a portion of the dual-layer sintered silver bonding structure. The dual-layer sintered silver bonding structure includes a first sintered silver layer positioned on the substrate, and a second sintered silver layer positioned on the first sintered silver layer, with the chip located on the second sintered silver layer. The first sintered silver layer has a porosity of less than 5%, and the second sintered silver layer has a Young's modulus of less than 20 GPa.