Dual-Layer SiON Etch Stop Film for MOS Transistor Reliability

Solution Overview

Problem

MOS transistors formed with high SiH4 flow rates during SiON etch stop layer deposition are susceptible to hot carrier injection, leading to premature degradation and functional failure due to increased hydrogen incorporation at the silicon-gate oxide interface, while low SiH4 flow rates provide inadequate conductivity against plasma-induced damage.

Innovation Solution

A dual-layer SiON etch stop film is formed with a lower layer having a SiH4 flow rate of 50 sccm to minimize hydrogen incorporation and a higher layer with a SiH4 flow rate of 120 sccm for enhanced conductivity, creating a barrier to prevent hydrogen from reaching the interface and reducing hot carrier degradation while maintaining adequate conductivity to prevent plasma-induced damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high SiH4 flow rate (120 sccm) is used during SiON etch stop layer deposition, then conductivity is enhanced and plasma-induced damage is prevented, but hot carrier injection increases leading to premature degradation

Engineering Contradiction:

Improveprotection against plasma-induced damageVSAvoidhot carrier degradation

Core Design Contradiction:

ReliabilityVSReliability

Solution Approach 1:

The patent divides the single-layer SiON etch stop layer into a dual-layer structure: a lower SiON layer deposited at low SiH4 flow rate (30-85 sccm) to minimize hydrogen incorporation and protect against hot carrier injection, and an upper SiON layer deposited at high SiH4 flow rate (110-120 sccm) to provide high conductivity and protect against plasma-induced damage. This segmentation allows each layer to optimize for its specific protective function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different deposition conditions to different portions of the SiON etch stop layer. The lower layer uses low SiH4 flow rate (30-85 sccm) to create a region with minimal hydrogen content near the sensitive silicon-gate oxide interface, while the upper layer uses high SiH4 flow rate (110-120 sccm) to create a region with high conductivity for plasma charge dissipation. Each layer has locally optimized properties for its specific protective role.

Inventive Principle:

Principle #3Local quality

2Reliability

If low SiH4 flow rate (50 sccm) is used during SiON etch stop layer deposition, then hot carrier degradation is reduced, but conductivity is insufficient to prevent plasma-induced damage

Engineering Contradiction:

Improveresistance to hot carrier degradationVSAvoidprotection against plasma-induced damage

Core Design Contradiction:

ReliabilityVSReliability

Solution Approach 1:

The patent divides the single-layer SiON etch stop layer into a dual-layer structure: a lower SiON layer deposited at low SiH4 flow rate (30-85 sccm) to minimize hydrogen incorporation and protect against hot carrier injection, and an upper SiON layer deposited at high SiH4 flow rate (110-120 sccm) to provide high conductivity and protect against plasma-induced damage. This segmentation allows each layer to optimize for its specific protective function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different deposition conditions to different portions of the SiON etch stop layer. The lower layer uses low SiH4 flow rate (30-85 sccm) to create a region with minimal hydrogen content near the sensitive silicon-gate oxide interface, while the upper layer uses high SiH4 flow rate (110-120 sccm) to create a region with high conductivity for plasma charge dissipation. Each layer has locally optimized properties for its specific protective role.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dual-layer SiON etch stop film significantly improves hot carrier reliability by reducing degradation and protecting against plasma-induced damage, extending the transistor's operational life and maintaining electrical integrity.

Implementation Method 1

the SiON layer provides a conductive path to ground that prevents plasma induced damage (PID). PID results when plasma etching is used, and can lead to the build up of a charge on the transistor gate that, if not discharged, can seriously damage or destroy the underlying gate oxide layer.

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

The TABLE below illustrates two SiON deposition recipes. In the Table, RI(n) is the film's index of refraction, and RI(k) is the film's extinction coefficient. However, the silane (SiH4) flow rate used during SiON film deposition is critical to controlling the effects of PID.

Methodology Applied

Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 3

A dual-layer SiON etch stop film is formed with a lower layer having a SiH4 flow rate of 50 sccm to minimize hydrogen incorporation and a higher layer with a SiH4 flow rate of 120 sccm for enhanced conductivity, creating a barrier to prevent hydrogen from reaching the interface and reducing hot carrier degradation

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS7645657B2MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation

Publication Date: 2010.01.12 NAT SEMICON CORP

AI summary

A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiH4 at a first flow rate, and the second SiON layer is formed with SiH4 at a second higher flow rate.