Dual-Layer Source/Drain Structure for Semiconductor Carrier Mobility
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Solution Overview
Problem
Semiconductor structures face challenges in simultaneously achieving high carrier mobility and low parasitic capacitance due to the conflicting effects of strained silicon technology on the channel region and parasitic capacitors formed by the gate, sidewall spacers, and doped source/drain layers.
Innovation Solution
A method and structure where a first doped source/drain layer is formed with a minimum distance to the gate structure, generating significant stress for high carrier mobility, and a second doped source/drain layer is formed with a greater distance, reducing parasitic capacitance, by adjusting the thickness and position of sidewall spacers to optimize both parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained silicon technology is introduced to increase carrier mobility by reducing the distance between doped source/drain layer and gate structure, then carrier mobility is improved, but parasitic capacitance increases
Solution Approach 1:
The source/drain structure is divided into two distinct layers: a first doped source/drain layer positioned close to the gate structure to maximize stress on the channel region and enhance carrier mobility, and a second doped source/drain layer positioned farther away to minimize parasitic capacitance. This segmentation allows each layer to fulfill different functional requirements that would be conflicting in a single-layer structure.
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping concentrations and positions optimized for their specific functions. The first layer has higher doping concentration and is positioned closer to the gate for maximum stress effect, while the second layer has appropriate doping and is positioned farther to reduce capacitance. This local optimization resolves the contradiction between mobility enhancement and parasitic capacitance reduction.
2Reliability
If the doped source/drain layer is positioned closer to the gate structure to generate more stress on the channel region, then carrier mobility increases, but the parasitic capacitance between source/drain and gate increases
Solution Approach 1:
The source/drain structure is divided into two distinct layers: a first doped source/drain layer positioned close to the gate structure to maximize stress on the channel region and enhance carrier mobility, and a second doped source/drain layer positioned farther away to minimize parasitic capacitance. This segmentation allows each layer to fulfill different functional requirements that would be conflicting in a single-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility while minimizing parasitic capacitance, thereby improving the overall performance of the semiconductor structure.
Implementation Method 1
The strained silicon technology causes the crystal lattice of the doped source/drain layer to be different from the crystal lattice of the semiconductor substrate so as to cause the doped source/drain layer to generate a stress to the channel region. Accordingly, the carrier mobility of the channel region is increased.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure on a top surface of the base substrate; and forming a first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the first doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a first distance. The method also includes forming a second doped source/drain layer on the first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the second doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a second distance; and the second distance is greater than the first distance.