Dual-Active-Layer TFT Structure for Threshold Voltage Stability
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Solution Overview
Problem
Existing thin film transistors (TFTs) face challenges with threshold voltage bias and power consumption due to undercut structures and oxygen vacancy defects, leading to negatively biased threshold voltages and hump characteristics in their performance curves.
Innovation Solution
The design incorporates a thin film transistor structure with overlapping regions between electrodes and active layers, where the second surface of the second active layer is within the first surface, and the third active layer is positioned to reduce undercut risks, using materials like indium gallium zinc oxide and praseodymium-doped indium zinc oxide to enhance mobility and stability, and a specific etching rate ratio to control layer thickness and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional thin film transistor structure is used, then the manufacturing process is simple, but the threshold voltage becomes negatively biased and power consumption increases due to undercut structures and oxygen vacancy defects
Solution Approach 1:
The active layer is segmented into multiple layers (first active layer and second active layer) with different materials and thicknesses. The first active layer contains indium gallium zinc oxide while the second contains praseodymium-doped indium zinc oxide. This segmentation allows each layer to contribute differently to carrier transport and threshold voltage control, preventing the negative bias issue while maintaining manufacturing feasibility through sequential deposition
Solution Approach 2:
Different regions of the active layer structure are given different local qualities through varying material composition and thickness. The first active layer has higher carrier mobility for efficient transport, while the second active layer with praseodymium doping provides stability and prevents oxygen vacancies. The gate electrode is positioned to overlap specifically with certain regions to enhance control over threshold voltage without causing negative bias
2Reliability
If the second surface of the second active layer is positioned within the first surface with small distance, then undercut risks are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The vertical positioning parameter of the second surface is controlled to be within the first surface with a specific distance range (less than or equal to 0.5 μm). This parameter change optimizes the overlap between active layer surfaces, reducing undercut risks while the manufacturing process controls the precision through calibrated deposition thicknesses and etching parameters
3Speed
If overlapping regions between electrodes and active layers are increased, then carrier mobility and response speed improve, but device complexity increases
Solution Approach 1:
The gate electrode is extended in the vertical dimension to overlap with both the first and second active layers. This dimensional extension creates overlapping regions that enhance electric field control and carrier mobility without requiring additional lateral electrodes or complex planar configurations, thus improving performance while maintaining relatively simple device structure
Data Source
AI summary
A thin film transistor includes a first active layer, a second active layer, a first electrode, a second electrode and a third electrode. The first active layer includes a first surface away from a substrate. The second active layer includes a second surface in contact with the first surface. The first electrode, the first active layer and the second active layer have an overlapping region. The second electrode, the first active layer and the second active layer have an overlapping region. The third electrode, the first active layer and the second active layer have an overlapping region, and the third electrode is opposite to the second electrode. The second surface is located within the first surface, and a distance between at least part of a border of the second surface and a border of the first surface is less than or equal to 0.5 μm.