Dual-Layered Semiconductor Chip Direct Bonding for Density
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in reducing the size and increasing the packing density of semiconductor chips while maintaining physical durability, as thinner chips are prone to defects and require additional processes for forming bumps and insulation.
Innovation Solution
A dual-layered structural semiconductor chip is fabricated by directly bonding two semiconductor chips with through electrodes, where each chip has a substrate with opposite top and bottom surfaces, and surface activation is used to facilitate bonding at room temperature, reducing thickness and eliminating the need for intervening layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of semiconductor chips is reduced to increase the number of chips vertically stacked, then the packing density is improved, but the physical durability is degraded leading to cracks
Solution Approach 1:
The invention divides a single thick chip into multiple thin chip layers, each with its own active components and interconnections. This segmentation allows the stack to achieve high packing density while each individual thin layer maintains structural integrity, preventing cracks that would occur in overly thin monolithic chips.
Solution Approach 2:
The invention uses composite structures where multiple chip layers are bonded together with intermediate bonding layers. This composite approach combines the advantages of thin chips (high density) with the strength of bonded assemblies, creating a structurally sound multi-layer package that maintains durability while achieving high stacking density.
2Reliability
If additional processes are added for forming bumps and insulating individual chips, then the electrical connections are improved, but the fabrication complexity increases
Solution Approach 1:
The invention merges multiple fabrication processes into unified steps. Through-silicon vias are formed through all chip layers simultaneously, and bonding pads are created in integrated fashion during the layer assembly process. This consolidation reduces the total number of separate processing steps while ensuring reliable electrical connections between layers.
Solution Approach 2:
The invention performs preliminary actions by pre-forming through-silicon vias and bonding pads in each chip layer before final assembly. This advance preparation of interconnection structures simplifies the final stacking and bonding process, as the electrical pathways are already established and aligned, reducing on-the-fly fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a thinner, more densely packed semiconductor chip with reduced interconnection lengths, enhancing durability and simplifying the fabrication process by eliminating the need for additional processes like wire bonding.
Implementation Method 1
surface activation is used to facilitate bonding at room temperature
Data Source
AI summary
Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.