Dual-Architecture Transistor Layout for BPR and Non-BPR Porting
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Solution Overview
Problem
Existing semiconductor design rules are specific to a single architecture, limiting the flexibility and adaptability of semiconductor devices to different power rail architectures, requiring additional patterns or extensions to accommodate changes.
Innovation Solution
A dual-architecture-compatible layout diagram that can be selectively pruned to yield either a non-buried power rail (non-BPR) or buried power rail (BPR) architecture without adding new patterns, by including dummy structures that facilitate adaptation to both architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design rules are specific to a single architecture, then manufacturing precision is improved for that architecture, but adaptability to different architectures deteriorates
Solution Approach 1:
The patent creates a universal layout diagram that can be adapted to multiple power rail architectures (both non-BPR and BPR types) through selective pattern removal. The layout includes dummy structures and configurable elements that allow the same base design to function across different architectural implementations, eliminating the need for separate design rules for each architecture.
Solution Approach 2:
The patent incorporates dummy structures and optional patterns in advance during the initial layout creation. These pre-placed elements can be selectively removed or retained depending on the target architecture, allowing seamless adaptation without requiring redesign. The dummy structures serve as placeholders that maintain design rule compliance for both architecture types simultaneously.
2Adaptability or versatility
If layout diagrams are extended to accommodate different architectures, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent enables architecture-specific adaptation by selectively removing (extracting) unnecessary patterns from the universal layout diagram. For non-BPR architectures, BPR-specific dummy structures are removed; for BPR architectures, non-BPR patterns are retained. This extraction approach maintains adaptability while avoiding the complexity of maintaining separate complete layouts for each architecture.
Solution Approach 2:
The layout diagram is segmented into mandatory core patterns and optional architecture-specific patterns. The core patterns remain unchanged across architectures, while the optional segments can be selectively enabled or disabled. This segmentation reduces overall complexity by clearly separating architecture-independent design elements from architecture-specific variations.
3Adaptability or versatility
If additional patterns are added to support multiple architectures, then adaptability is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies different pattern sets to different local regions of the layout based on architectural requirements. Dummy structures are placed in specific locations where they are needed for BPR architecture compliance but can be removed for non-BPR implementations. This localized approach ensures that manufacturing precision is maintained for the active patterns while providing adaptability through selective local modifications.
Data Source
AI summary
A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.