Dual LDO Regulator Memory Power Management
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Solution Overview
Problem
SRAM circuits face challenges in reducing power consumption while maintaining performance, especially in consumer electronics where increased voltage operation shortens battery life and smaller transistor gate-oxides require higher threshold voltages, making it difficult to manage power efficiently during active and standby modes.
Innovation Solution
A memory power management system using two low dropout (LDO) regulators to provide an active operating voltage and a minimum memory retention voltage, along with selectably coupleable diodes to manage power in memory blocks, allowing for tri-state mode operation and reducing power consumption in both memory arrays and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If increased voltage operation is used to achieve greater speeds, then processing speed is improved, but power consumption increases and battery life is shortened
Solution Approach 1:
The patent implements dynamic voltage scaling by providing different voltage levels to different memory blocks based on their operational state. Active memory blocks receive higher voltage for fast operation, while standby blocks receive lower voltage to reduce power consumption. This dynamic adjustment resolves the contradiction between speed and power consumption by allowing the system to optimize voltage levels in real-time based on actual memory access patterns.
Solution Approach 2:
The memory array is divided into multiple independently controllable memory blocks, each with its own voltage control. This segmentation allows selective voltage application where only actively accessed memory blocks receive high voltage, while other blocks operate at reduced voltage or are powered down. This resolves the contradiction by localizing high-power operation to only the necessary portions of the memory system.
2Manufacturing precision
If smaller transistor gate-oxides are used to increase integration density, then manufacturing precision is improved, but threshold voltage requirements increase making power management more difficult
Solution Approach 1:
The patent applies different voltage levels to different memory blocks based on their operational requirements. Smaller transistor gate-oxides are accommodated by providing locally optimized voltage levels - higher voltage where needed for reliable operation of small transistors, and lower voltage where possible to reduce power consumption. This local quality approach resolves the contradiction by allowing precise voltage control matched to the specific characteristics of each memory block's transistors.
3Device complexity
If a single voltage level is used for the memory array, then device complexity is reduced, but power consumption cannot be optimized during standby operations
Solution Approach 1:
The system dynamically switches between single-voltage and multi-voltage modes based on operational requirements. During active operations, the entire memory array can operate at a single high voltage level for simplicity and performance. During standby operations, the system transitions to multi-voltage mode where inactive blocks receive reduced voltage, optimizing power consumption. This dynamic approach resolves the contradiction between complexity and power optimization.
Solution Approach 2:
The voltage control system is designed to provide both single-voltage and multi-voltage operation capabilities through a unified architecture. The same control circuitry can switch between providing a single voltage level to all memory blocks or providing different voltage levels to different blocks, making the system universal and adaptable to different operational modes without requiring separate dedicated circuits for each mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable data retention and reduced power consumption by providing appropriate voltages for active and standby modes, extending battery life and improving manufacturing yield in SRAM circuits with small transistor gate sizes.
Implementation Method 1
a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode
Implementation Method 2
selectably coupling a respective selectably coupleable diode to each of a plurality of memory blocks of the memory array to provide a minimum memory retention voltage to power each of the plurality of memory blocks
Data Source
AI summary
Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.