Dual LDPC FEC Cascade for Reliable Fiber-Optic Transceivers

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Solution Overview

Problem

Fiber-optic networks face data corruption issues due to noise and intersymbol interference, leading to bit errors and erasures during data transmission, which existing systems struggle to address effectively, especially as data transmission rates increase.

Innovation Solution

The implementation of a transceiver system with a fiber-optic interface unit and a host unit, featuring dual forward error correction (FEC) decoders - a soft-decision input LDPC decoder at the fiber-optic interface unit and a hard-decision input LDPC decoder at the host unit - that work in cascade to correct bit errors and maintain reliable data transmission by leveraging increased coding gain and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission rate is increased in fiber-optic networks, then productivity is improved, but bit errors and data corruption increase due to noise and intersymbol interference

Engineering Contradiction:
Improvedata transmission rateVSAvoiddata transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The error correction function is segmented into two distinct stages: a first FEC decoder at the physical layer and a second FEC decoder at the data link layer. Each decoder handles different aspects of error correction, with the first decoder addressing physical transmission errors and the second decoder handling residual errors, enabling high-speed transmission while maintaining reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first FEC decoder performs preliminary error correction on received data before it reaches the data link layer. By pre-correcting errors at the physical layer, the system reduces the error burden on higher layers, enabling reliable high-speed transmission without requiring complete retransmission protocols

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a single high-complexity FEC decoder is used to correct all bit errors, then reliability is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex error correction task is divided between two decoders with different complexity levels. The first FEC decoder handles the most difficult error correction at the physical layer, while the second FEC decoder at the data link layer handles residual errors with simpler algorithms, reducing overall system complexity while maintaining high reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first FEC decoder performs partial error correction, correcting the most significant errors at the physical layer. The second FEC decoder then performs additional correction on the already-partially-corrected data, achieving complete error correction through staged partial actions rather than requiring a single overly complex decoder

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If a single high-complexity FEC decoder is used to ensure reliable data transmission, then reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The power-intensive error correction function is segmented into two stages with different power requirements. The first FEC decoder consumes more power to handle severe physical layer errors, while the second FEC decoder consumes less power for residual error correction, reducing total power consumption compared to using a single high-power decoder for all correction tasks

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first FEC decoder performs partial error correction at the physical layer, reducing the error burden before data reaches the data link layer. The second FEC decoder then performs partial correction on the already-improved data, achieving complete error correction through staged partial actions that consume less total power than a single exhaustive correction approach

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250023584A1PMD-to-TC-mac interface with 2-stage FEC protection
Publication Date: 2025.01.16 MAXLINEAR INC
  • US20250023584A1 patent drawing
  • US20250023584A1 patent drawing
  • US20250023584A1 patent drawing

AI summary

A system for a fiber-optic network includes a transceiver. The transceiver includes a fiber-optic interface unit and a host unit. The host unit includes a low-complexity error correction decoder and a high-complexity error correction decoder. One or both from the low-complexity error correction decoder and the high-complexity error correction decoder are selected to decode input data from the fiber-optic interface unit, the input data including codewords.