Dual Leadframe GaN Packaging for Low Inductance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional packaging solutions for lateral GaN power transistors face challenges such as high inductance, insufficient current handling, and thermal management issues, which limit the size and performance of power transistors, and are not optimized for the unique characteristics of GaN-on-Si dies.
Innovation Solution
A dual leadframe packaging structure where the GaN die is sandwiched between first and second leadframe layers, with low inductance interconnections and a thermal pad for effective thermal management, eliminating wirebonding and providing improved current handling and reduced inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wirebond packaging is used for lateral GaN power transistors, then manufacturing simplicity is maintained, but inductance increases and current handling capability deteriorates
Solution Approach 1:
The patent extracts and eliminates the wirebond interconnection layer from the packaging structure. By directly bonding the GaN die to the leadframe using eutectic bonding, the wirebonds are removed entirely, reducing inductance and simplifying the current path while maintaining manufacturing feasibility through standardized bonding processes.
Solution Approach 2:
The patent merges the die-attach function and the electrical interconnection function into a single direct bond interface. The GaN die is bonded directly to the leadframe contact pads, combining what were previously separate functions (wirebond for electrical connection, eutectic attach for mechanical support) into one integrated low-inductance connection.
2Reliability
If larger area contact pads are provided around the periphery of the chip, then current handling capacity is improved, but on-chip metallization resistance increases and inductance worsens
Solution Approach 1:
The patent transitions from planar peripheral contact pads to a three-dimensional stacked architecture. Contact pads are distributed across multiple layers (source/drain/gate pads on die, corresponding pads on leadframe), creating vertical current paths that reduce the horizontal distance current must travel through high-resistance metallization, thereby reducing resistive losses while maintaining high current capacity.
Solution Approach 2:
The patent segments the contact pads into multiple discrete locations distributed across the die surface and leadframe layers. Instead of relying on a few large peripheral pads with long current paths, multiple smaller pads are strategically positioned to create shorter, parallel current paths, reducing both resistance and inductance while maintaining total current handling capacity.
3Temperature
If conventional power module packaging is used, then manufacturing standardization is maintained, but thermal management effectiveness deteriorates for GaN-on-Si dies
Solution Approach 1:
The patent changes the thermal conduction path parameters by creating a direct, low-thermal-resistance bond between the GaN die and the leadframe. The eutectic bonding process creates a metallurgical bond with superior thermal conductivity compared to conventional die-attach materials, and the direct bond eliminates intermediate thermal interfaces, significantly improving heat dissipation efficiency.
Solution Approach 2:
The patent employs a composite packaging structure combining the GaN die, eutectic bonding material, and copper leadframe. This composite architecture leverages the high thermal conductivity of copper in the leadframe and the metallurgical bond quality of eutectic joining to create an optimized thermal management system that exceeds the performance of conventional homogeneous packaging materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables larger GaN power devices with reduced inductance and improved thermal dissipation, allowing for higher current handling and more compact designs while maintaining cost-effectiveness.
Implementation Method 1
the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of the first leadframe layer using low inductance interconnections
Implementation Method 2
the second leadframe layer comprising a thermal pad and providing a die-attach area for the back surface of the GaN die
Data Source
AI summary
Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.