Dual-Level Branch Target Cache for Processor Performance

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing data processing apparatuses face challenges in providing accurate target address information for branch instructions, particularly with indirect branches, due to limited branch target cache sizes, which impact processor performance and increase area and power consumption.

Innovation Solution

A dual-level branch target cache structure is implemented, with an initial entry branch target cache and a promoted entry branch target cache accessed in parallel, where branch instruction information is initially allocated to the initial cache and promoted to the secondary cache based on a promotion threshold condition, ensuring retention of valuable information without complicating the replacement mechanism.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the branch target cache size is increased to improve retention of branch instruction information, then processor performance is improved, but area and power consumption increase

Engineering Contradiction:

Improveretention of branch instruction informationVSAvoidcache structure area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The branch target cache is segmented into two distinct levels: an initial entry branch target cache for new allocations and a promoted entry branch target cache for retained information. This segmentation allows the system to maintain larger effective cache capacity while keeping each individual cache structure compact, thereby improving retention without proportionally increasing total area.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to cache management by promoting entries from the initial cache to the promoted cache based on usage patterns. This two-level hierarchical structure adds a dimension of cache lifecycle management, allowing the system to retain useful information longer without requiring a single large cache structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the branch target cache size is increased to improve retention of branch instruction information, then processor performance is improved, but power consumption increases

Engineering Contradiction:

Improveretention of branch instruction informationVSAvoidcache structure power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

By dividing the cache into two smaller, specialized structures rather than one large cache, the system reduces the power consumption associated with maintaining a single large cache structure. Each cache can be optimized for its specific function, reducing overall power requirements while maintaining effective retention capacity.

Inventive Principle:

Principle #1Segmentation

3Device complexity

If a single-level branch target cache is used with simple allocation, then device complexity is reduced, but retention of useful branch instruction information deteriorates

Engineering Contradiction:

Improvecache allocation mechanismVSAvoidretention of useful branch instruction information

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The dual-level cache structure separates the concerns of new allocation (initial cache) and retention (promoted cache). This segmentation allows each cache to have simple, specialized allocation rules while the system as a whole achieves sophisticated retention behavior without complicating individual allocation mechanisms.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The promoted entry cache automatically retains information that has proven useful through the promotion mechanism, eliminating the need for complex replacement policies. Useful entries self-organize into the promoted cache where they are protected from eviction, simplifying the overall replacement mechanism while improving retention.

Inventive Principle:

Principle #25Self-service

4Productivity

If parallel access to both caches is implemented, then lookup operation efficiency is maintained, but device complexity increases

Engineering Contradiction:

Improvelookup operation efficiencyVSAvoiddual-level cache structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the functionality of two caches with parallel access into a unified branch target cache structure. The initial cache and promoted cache work together as an integrated system, sharing control logic and access mechanisms, which reduces the complexity that would arise from completely independent parallel cache structures.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8635406B2Data processing apparatus and method for providing target address information for branch instructions

Publication Date: 2014.01.21 ARM LTD

AI summary

A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.