Dual-Level ECC Word Layout for MRAM Error Correction
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Solution Overview
Problem
Memory devices, particularly magnetic random access memories (MRAMs), experience higher inherent random errors during access operations compared to dynamic random access memories (DRAMs), leading to inefficiencies in error correction and system-level error correction challenges.
Innovation Solution
Implementing a dual-level error correction system within memory devices, where the first level corrects errors at the device level and the second level corrects errors at the system level, with orthogonal error correction mechanisms to improve error handling and processing efficiency by distributing error correction across multiple input/output pads and ECC words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-level error correction system is used in memory devices, then the device complexity is reduced, but the reliability of error correction deteriorates due to higher error rates in MRAM compared to DRAM
Solution Approach 1:
The error correction system is divided into two independent levels: device-level ECC circuitry within the memory device and system-level ECC circuitry in the external device. Each level handles a portion of the error correction task, with the device-level correcting errors in individual ECC words and the system-level correcting remaining errors across multiple I/O pads. This segmentation allows the system to achieve higher reliability without overwhelming complexity at any single point.
Solution Approach 2:
The error correction mechanisms are nested hierarchically with device-level ECC operating within each ECC word and system-level ECC operating across multiple ECC words and I/O pads. The system-level ECC is designed to work with and complement the device-level ECC, creating a nested structure where each level provides an additional layer of error protection.
2Reliability
If error correction is performed at every I/O pad, then the reliability improves, but the processing speed deteriorates due to increased correction overhead
Solution Approach 1:
Instead of performing full error correction at every I/O pad simultaneously, the system performs partial error correction at the device level for each ECC word, then performs additional correction at the system level for remaining errors. This partial action approach at each level achieves complete error correction without the excessive processing overhead of attempting to correct all errors at a single level.
3Reliability
If multiple errors occur in the same ECC word, then the device-level ECC fails to correct them, but passing all errors to system-level ECC worsens the correction capability due to error distribution across multiple I/O pads
Solution Approach 1:
The system segments the error correction task across two levels: device-level ECC handles errors within individual ECC words, while system-level ECC handles errors that span multiple ECC words and I/O pads. This segmentation ensures that even when multiple errors occur in the same ECC word and exceed device-level correction capability, the system-level ECC can still correct them by operating on the distributed error pattern across multiple I/O pads.
Data Source
AI summary
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.