Dual-Level X-Masking in Test Response Compactors
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Solution Overview
Problem
Existing test response compaction techniques struggle with unknown states (X bits) in scan-based semiconductor device testing, leading to deteriorated test quality and inefficiencies in manufacturing tests, particularly in safety-critical applications.
Innovation Solution
A dual-level X-masking circuitry is implemented in the test response compactor, comprising first X-masking circuitry operating in a per test pattern mode and second X-masking circuitry operating in a per clock cycle mode, to effectively filter out unknown states using both spatial and temporal compaction methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If X-masking is applied to filter out unknown states, then test quality is improved, but test logic complexity and data volume increase
Solution Approach 1:
The patent divides the single X-masking operation into two distinct stages: first X-masking circuitry that operates per test pattern, and second X-masking circuitry that operates per clock cycle. This segmentation allows each stage to handle specific aspects of X-bit filtering, improving overall test quality while managing complexity through functional decomposition
Solution Approach 2:
The patent introduces a temporal dimension to X-masking by implementing per-clock-cycle masking in addition to per-test-pattern masking. This transforms the problem from a purely spatial operation to a spatio-temporal operation, enabling more effective X-bit filtering without proportionally increasing logic complexity
2Reliability
If per-clock-cycle X-masking is implemented, then unknown states are better filtered, but test data volume increases
Solution Approach 1:
The patent extracts and removes X-bits from the test data stream at two different stages: first extracting X-bits on a per-pattern basis, then extracting remaining X-bits on a per-clock-cycle basis. This extraction approach prevents X-bits from proliferating through the compactor while minimizing the addition of control data
Solution Approach 2:
The first X-masking circuitry performs preliminary filtering of X-bits before the data enters the second X-masking stage. This preliminary action reduces the burden on the second stage and minimizes the total amount of data that needs to be processed and controlled
3Measurement precision
If multiple masking stages are used, then diagnostic resolution is improved, but manufacturing test time increases
Solution Approach 1:
The patent implements continuous X-masking throughout the test process by operating the first and second X-masking circuitry in sequence without interruption. The per-test-pattern masking operates continuously for each pattern, and the per-clock-cycle masking operates continuously during the shift-out phase, ensuring X-bits are filtered without stopping the test flow
Solution Approach 2:
The patent employs dynamic masking strategies where the first X-masking operates at the test pattern level and the second X-masking operates at the clock cycle level. This dynamic, multi-level approach adapts to the specific needs of different test phases, improving diagnostic resolution while minimizing time overhead
Data Source
AI summary
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.


