Dual-Line FIFO Latch-Flip-Flop Structure Without Multiplexers
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Solution Overview
Problem
Conventional dual-line FIFO memory elements in electronic devices consume significant circuit area and power due to the use of multiplexers, which becomes a resource-intensive issue when numerous FIFOs are required in systems-on-a-chip (SOC) circuits.
Innovation Solution
A dual-line FIFO structure is designed without a multiplexer, utilizing a selectively transparent latch and a flip-flop serially connected to temporarily store up to two data units, reducing the number of transistors and circuit area, and incorporating control circuitry to manage data transfer and storage efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multiplexer-based FIFO memory elements are used, then data synchronization function is achieved, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the multiplexer component from the conventional FIFO structure. Instead of using a multiplexer to select between two flip-flop outputs, the invention uses a single flip-flop with a transparent latch that can directly output data when enabled, eliminating the need for the multiplexer and its associated circuit area and power consumption.
Solution Approach 2:
The patent merges the functions of the multiplexer and the flip-flop output stage into a single transparent latch mechanism. The latch can transparently pass data to the output when enabled, combining the selection and output functions into one component, thereby reducing overall circuit complexity and resource usage.
2Reliability
If conventional multiplexer-based FIFO memory elements are used, then data synchronization function is achieved, but power consumption increases significantly
Solution Approach 1:
The patent extracts and removes the multiplexer component from the conventional FIFO structure. Instead of using a multiplexer to select between two flip-flop outputs, the invention uses a single flip-flop with a transparent latch that can directly output data when enabled, eliminating the need for the multiplexer and its associated circuit area and power consumption.
Solution Approach 2:
The transparent latch is self-controlled through the fill status signal. When the FIFO is not full, the latch automatically becomes transparent and allows data to pass through without requiring additional control logic or power-consuming selection mechanisms. The system serves itself by using the fill status to directly control the latch transparency.
3Adaptability or versatility
If numerous FIFOs are deployed in SOC circuits, then data buffering capability is improved, but resource utilization deteriorates due to multiplexer overhead
Solution Approach 1:
The patent extracts and removes the multiplexer component from the conventional FIFO structure. Instead of using a multiplexer to select between two flip-flop outputs, the invention uses a single flip-flop with a transparent latch that can directly output data when enabled, eliminating the need for the multiplexer and its associated circuit area and power consumption.
Solution Approach 2:
The patent changes the fundamental operating parameter of the FIFO from using parallel flip-flops with multiplexer selection to using a single flip-flop with sequential transparent latch operation. This parameter change in the architectural approach allows for more efficient resource utilization when deploying multiple FIFOs in SOC circuits.
Data Source
AI summary
Embodiments described herein provide a dual-line FIFO structure without the use of any multiplexer. Instead, the dual-line FIFO described herein uses a selectively transparent latch and a flip-flop serially connected to the latch, such that the combination of the serially connected latch and the flip-flop can temporarily store up to two data units at two clock cycles.