Dual Dielectric Liner Structure for Punch-Through Leakage Control
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Solution Overview
Problem
Existing semiconductor structures face challenges in controlling punch through leakage, which degrades device performance due to positive defect charges in dielectric liners, particularly in FinFET and nanosheet FET devices.
Innovation Solution
The use of different dielectric liners on different regions of semiconductor layers, surrounded by shallow trench isolation regions, to control punch through leakage by altering the charge distribution and distance between the liners and channel regions, tailored for n-type and p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single type of dielectric liner is used surrounding the semiconductor layer, then the manufacturing process is simple, but punch through leakage cannot be effectively controlled
Solution Approach 1:
The dielectric liner is segmented into multiple types: a first dielectric liner surrounding the channel region and a second dielectric liner surrounding the punch through stop region. This segmentation allows each liner type to be optimized for its specific function, with the first liner controlling interface quality at the channel and the second liner providing electrical isolation at the punch through stop, thereby effectively reducing punch through leakage.
Solution Approach 2:
Different dielectric materials are applied to different regions of the semiconductor structure. The first dielectric liner uses material optimized for interface quality with the channel region, while the second dielectric liner uses material optimized for electrical isolation properties at the punch through stop region. This local quality differentiation enables precise control of punch through leakage while maintaining manufacturing feasibility.
2Area of stationary object
If the dielectric liner is placed close to the channel region, then the device area is reduced, but punch through leakage increases due to positive defect charges
Solution Approach 1:
The first dielectric liner acts as an intermediary layer between the semiconductor channel region and the surrounding environment. It is specifically positioned adjacent to the channel region and engineered with appropriate material properties to minimize positive defect charges while maintaining electrical isolation, thus preventing punch through leakage even when placed close to the channel.
Solution Approach 2:
The material parameters of the dielectric liners are optimized to change the charge distribution characteristics. By selecting dielectric materials with specific properties and adjusting their thickness, the positive defect charge density is reduced, allowing the liner to be placed closer to the channel region without increasing punch through leakage.
Data Source
AI summary
A semiconductor structure includes a semiconductor layer, one or more channel layers disposed over the semiconductor layer, a first dielectric liner surrounding sidewalls of a first region of the semiconductor layer proximate the one or more channel layers, a second dielectric liner surrounding sidewalls of a second region of the semiconductor layer below the first region of the semiconductor layer, and a shallow trench isolation region surrounding the first dielectric liner and the second dielectric liner, where the first dielectric liner and the second dielectric liner are different materials.