Dual Load Buffer Parallel Processing Architecture
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Solution Overview
Problem
Current processing architectures are often poorly suited for handling vast datasets, leading to inefficiencies and throughput limitations in executing complex processing jobs, particularly in tasks that require simultaneous data loading, processing, and storage across multiple compute elements.
Innovation Solution
A parallel processing architecture with dual load buffers is implemented, utilizing a two-dimensional array of compute elements with two data caches that support a common address space, allowing for simultaneous data loading and execution, and maintaining coherence between caches through precedence information and parallel data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single data cache is used to supply data to compute elements, then the device complexity is reduced, but the data load bandwidth is limited and propagation delays increase
Solution Approach 1:
The data cache is divided into multiple independent caches (first data cache and second data cache), each serving different portions of the compute element array. This segmentation increases data load bandwidth by allowing simultaneous data loading from multiple caches to different compute element portions, while each individual cache maintains manageable complexity.
Solution Approach 2:
The system transitions from a single-cache architecture to a multi-cache architecture, adding a dimensional aspect to data loading. Multiple caches operate in parallel along the spatial dimension of the compute element array, enabling simultaneous data supply to different regions and effectively increasing bandwidth without proportionally increasing overall system complexity.
2Speed
If data is loaded sequentially to compute elements, then the device complexity is reduced, but the propagation delays increase and processing efficiency decreases
Solution Approach 1:
Data is pre-loaded into the first and second data caches before being supplied to the compute element array. This preliminary action allows data to be staged in advance in parallel cache structures, reducing the time data needs to traverse through the system during actual computation and thereby reducing propagation delays.
Solution Approach 2:
The multiple data caches enable continuous data supply to different portions of the compute element array simultaneously. While one portion is being processed, another portion is being loaded with data, ensuring that compute elements continuously have data available without idle waiting time, thus maintaining continuous useful action and reducing overall propagation delay.
3Productivity
If multiple data caches support a common address space, then the data load bandwidth is enhanced, but maintaining cache coherence becomes more complex
Solution Approach 1:
The system implements cache coherence mechanisms that provide feedback between the first and second data caches. When data is loaded or modified in one cache, coherence protocols ensure that the other cache is notified and updates its state accordingly. This feedback mechanism maintains data consistency across the common address space while allowing parallel data loading operations to proceed.
Solution Approach 2:
A coherence management system acts as an intermediary between the multiple data caches sharing the common address space. This intermediary coordinates data access and modification operations across caches, ensuring that simultaneous data loading from multiple caches does not create inconsistency, thereby enabling high throughput while managing coherence complexity through a dedicated coordination layer.
Data Source
AI summary
Techniques for parallel processing based on a parallel processing architecture with dual load buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A first data cache is coupled to the array. The first data cache enables loading data to a first portion of the array. The first data cache supports an address space. A second data cache is coupled to the array. The second data cache enables loading data to a second portion of the array. The second data cache supports the address space. Instructions are executed within the array. Instructions executed within the first portion of the array of compute elements use data loaded from the first data cache, and instructions executed within the second portion of the array of compute elements use data loaded from the second data cache.