Dual Lock Step Processor Differential Encoding Cybersecurity
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Solution Overview
Problem
Existing security systems in critical embedded systems are vulnerable to flaws that allow attackers to manipulate software, leading to control flow hijacking and arbitrary code execution, with the traditional vulnerability discovery-patch-update loop being slow and expensive, failing to provide effective cyber defense.
Innovation Solution
A dual lock step processor system comprising two processors and an exploit monitor, where each processor differentially encodes and decodes program values, ensuring that any mismatch in decoded values signals an issue, preventing unauthorized control and arbitrary code execution by running identical code in parallel and detecting any divergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional vulnerability discovery-patch-update loop is used, then system security is maintained through updates, but the response time is too slow and cost is too high to provide effective cyber defense
Solution Approach 1:
The system performs preliminary security validation by executing encoded instructions through multiple encoding paths before actual system operation. The differential encoding scheme pre-prepares multiple encoded versions of security-critical instructions, and the exploit monitor pre-validates their consistency, so that when an exploit attempt occurs, the system has already established a baseline of expected instruction behavior and can detect deviations immediately without waiting for vulnerability discovery and patching cycles.
2Reliability
If dual lock step processor system with differential encoding is implemented, then cybersecurity is significantly enhanced and unauthorized code execution is prevented, but device complexity increases
Solution Approach 1:
The system employs asymmetric differential encoding where two different encoding schemes are applied to the same instruction set. The first processor uses a first differential encoding scheme while the second processor uses a second differential encoding scheme. This asymmetry creates divergent encoded representations that must both validate correctly for the instruction to execute, providing strong security against code injection while maintaining a relatively simple overall architecture through the use of standard processor components.
Solution Approach 2:
The system creates redundant copies of the processor architecture with identical functional units but different encoding schemes. Instead of creating a single complex secure processor, two copies of a standard processor are used, each executing the same instruction set but with different differential encoding. The exploit monitor compares results from both copies, providing security through redundancy rather than through complex security mechanisms in a single processor.
3Reliability
If differential encoding and decoding is performed on all program values, then any mismatch signals an issue preventing exploits, but computational overhead increases
Solution Approach 1:
The system applies differential encoding selectively to specific instruction types and data paths rather than uniformly to all program values. The exploit monitor focuses its comparison operations on critical security paths where exploit attempts are most likely to occur, such as control flow instructions and memory access operations. This localized application of encoding and monitoring reduces the overall computational overhead while maintaining strong exploit detection capability where it is most needed.
Data Source
AI summary
A dual lock step processor system includes a first processor connected to a first memory, a second processor connected to a second memory, compiler engine, a first instruction engine operably connected to a first memory, and a second instruction engine operably connected to a second memory. The first instruction engine is configured to store a program value; encode the first program value using a first differential encoding and the compiler engine to generate a first encoded program value; and write the first encoded program value into a first address location of a plurality of first address locations. The second instruction engine is configured to store a program value; to encode the first program value using a second differential encoding and the compiler engine to generate a second encoded program value and write the second encoded program value into a second address location of a plurality of second address locations corresponding to the first selected address location.